diff --git a/rtl/axi_adapter_rd.v b/rtl/axi_adapter_rd.v
index a51881f90..3069934fb 100644
--- a/rtl/axi_adapter_rd.v
+++ b/rtl/axi_adapter_rd.v
@@ -474,14 +474,14 @@ always @* begin
                     m_axi_arregion_next = s_axi_arregion;
                     m_axi_aruser_next = s_axi_aruser;
                     m_axi_arvalid_next = 1'b1;
-                    m_axi_rready_next = s_axi_rready_int_early;
+                    m_axi_rready_next = 1'b0;
                     state_next = STATE_DATA;
                 end else begin
                     state_next = STATE_IDLE;
                 end
             end
             STATE_DATA: begin
-                m_axi_rready_next = s_axi_rready_int_early;
+                m_axi_rready_next = s_axi_rready_int_early && !m_axi_arvalid;
 
                 if (m_axi_rready && m_axi_rvalid) begin
                     data_next[addr_reg[S_ADDR_BIT_OFFSET-1:M_ADDR_BIT_OFFSET]*SEGMENT_DATA_WIDTH +: SEGMENT_DATA_WIDTH] = m_axi_rdata;
@@ -530,6 +530,7 @@ always @* begin
                                 m_axi_arsize_next = burst_size_reg;
                             end
                             m_axi_arvalid_next = 1'b1;
+                            m_axi_rready_next = 1'b0;
                             state_next = STATE_DATA;
                         end
                     end else begin
diff --git a/rtl/axi_adapter_wr.v b/rtl/axi_adapter_wr.v
index b15234df6..70cfb01b1 100644
--- a/rtl/axi_adapter_wr.v
+++ b/rtl/axi_adapter_wr.v
@@ -542,7 +542,7 @@ always @* begin
                     addr_next = addr_reg + (1 << master_burst_size_reg);
                     if (master_burst_reg == 0) begin
                         s_axi_wready_next = 1'b0;
-                        m_axi_bready_next = !s_axi_bvalid;
+                        m_axi_bready_next = !s_axi_bvalid && !s_axi_awvalid;
                         m_axi_wlast_int = 1'b1;
                         state_next = STATE_RESP;
                     end else if (addr_next[burst_size_reg] != addr_reg[burst_size_reg]) begin
@@ -569,7 +569,7 @@ always @* begin
                     if (master_burst_reg == 0) begin
                         // burst on master interface finished; transfer response
                         s_axi_wready_next = 1'b0;
-                        m_axi_bready_next = !s_axi_bvalid;
+                        m_axi_bready_next = !s_axi_bvalid && !m_axi_awvalid;
                         m_axi_wlast_int = 1'b1;
                         state_next = STATE_RESP;
                     end else if (addr_next[burst_size_reg] != addr_reg[burst_size_reg]) begin
@@ -584,7 +584,7 @@ always @* begin
             end
             STATE_RESP: begin
                 // resp state; transfer write response
-                m_axi_bready_next = !s_axi_bvalid;
+                m_axi_bready_next = !s_axi_bvalid && !m_axi_awvalid;
 
                 if (m_axi_bready && m_axi_bvalid) begin
                     first_transfer_next = 1'b0;