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Backpressure updates
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@ -474,14 +474,14 @@ always @* begin
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m_axi_arregion_next = s_axi_arregion;
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m_axi_aruser_next = s_axi_aruser;
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m_axi_arvalid_next = 1'b1;
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m_axi_rready_next = s_axi_rready_int_early;
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m_axi_rready_next = 1'b0;
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state_next = STATE_DATA;
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end else begin
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state_next = STATE_IDLE;
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end
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end
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STATE_DATA: begin
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m_axi_rready_next = s_axi_rready_int_early;
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m_axi_rready_next = s_axi_rready_int_early && !m_axi_arvalid;
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if (m_axi_rready && m_axi_rvalid) begin
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data_next[addr_reg[S_ADDR_BIT_OFFSET-1:M_ADDR_BIT_OFFSET]*SEGMENT_DATA_WIDTH +: SEGMENT_DATA_WIDTH] = m_axi_rdata;
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@ -530,6 +530,7 @@ always @* begin
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m_axi_arsize_next = burst_size_reg;
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end
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m_axi_arvalid_next = 1'b1;
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m_axi_rready_next = 1'b0;
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state_next = STATE_DATA;
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end
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end else begin
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@ -542,7 +542,7 @@ always @* begin
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addr_next = addr_reg + (1 << master_burst_size_reg);
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if (master_burst_reg == 0) begin
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s_axi_wready_next = 1'b0;
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m_axi_bready_next = !s_axi_bvalid;
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m_axi_bready_next = !s_axi_bvalid && !s_axi_awvalid;
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m_axi_wlast_int = 1'b1;
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state_next = STATE_RESP;
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end else if (addr_next[burst_size_reg] != addr_reg[burst_size_reg]) begin
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@ -569,7 +569,7 @@ always @* begin
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if (master_burst_reg == 0) begin
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// burst on master interface finished; transfer response
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s_axi_wready_next = 1'b0;
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m_axi_bready_next = !s_axi_bvalid;
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m_axi_bready_next = !s_axi_bvalid && !m_axi_awvalid;
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m_axi_wlast_int = 1'b1;
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state_next = STATE_RESP;
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end else if (addr_next[burst_size_reg] != addr_reg[burst_size_reg]) begin
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@ -584,7 +584,7 @@ always @* begin
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end
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STATE_RESP: begin
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// resp state; transfer write response
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m_axi_bready_next = !s_axi_bvalid;
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m_axi_bready_next = !s_axi_bvalid && !m_axi_awvalid;
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if (m_axi_bready && m_axi_bvalid) begin
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first_transfer_next = 1'b0;
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