merged changes in eth

fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v

@@ -56,6 +56,8 @@ module axis_async_fifo #
     parameter USER_ENABLE = 1,
     // tuser signal width
     parameter USER_WIDTH = 1,
+    // number of output pipeline registers
+    parameter PIPELINE_OUTPUT = 2,
     // Frame FIFO mode - operate on frames instead of cycles
     // When set, m_axis_tvalid will not be deasserted within a frame
     // Requires LAST_ENABLE set
@@ -119,6 +121,11 @@ parameter ADDR_WIDTH = (KEEP_ENABLE && KEEP_WIDTH > 1) ? $clog2(DEPTH/KEEP_WIDTH
 
 // check configuration
 initial begin
+    if (PIPELINE_OUTPUT < 1) begin
+        $error("Error: PIPELINE_OUTPUT must be at least 1 (instance %m)");
+        $finish;
+    end
+
     if (FRAME_FIFO && !LAST_ENABLE) begin
         $error("Error: FRAME_FIFO set requires LAST_ENABLE set (instance %m)");
         $finish;
@@ -147,68 +154,81 @@ localparam DEST_OFFSET = ID_OFFSET   + (ID_ENABLE   ? ID_WIDTH   : 0);
 localparam USER_OFFSET = DEST_OFFSET + (DEST_ENABLE ? DEST_WIDTH : 0);
 localparam WIDTH       = USER_OFFSET + (USER_ENABLE ? USER_WIDTH : 0);
 
-reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_next;
+reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}};
-reg [ADDR_WIDTH:0] wr_ptr_cur_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_cur_next;
+reg [ADDR_WIDTH:0] wr_ptr_cur_reg = {ADDR_WIDTH+1{1'b0}};
-reg [ADDR_WIDTH:0] wr_ptr_gray_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_gray_next;
+reg [ADDR_WIDTH:0] wr_ptr_gray_reg = {ADDR_WIDTH+1{1'b0}};
-reg [ADDR_WIDTH:0] wr_ptr_sync_gray_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_sync_gray_next;
+reg [ADDR_WIDTH:0] wr_ptr_sync_gray_reg = {ADDR_WIDTH+1{1'b0}};
-reg [ADDR_WIDTH:0] wr_ptr_cur_gray_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_cur_gray_next;
+reg [ADDR_WIDTH:0] wr_ptr_cur_gray_reg = {ADDR_WIDTH+1{1'b0}};
-reg [ADDR_WIDTH:0] wr_addr_reg = {ADDR_WIDTH+1{1'b0}};
+reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}};
-reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}}, rd_ptr_next;
+reg [ADDR_WIDTH:0] rd_ptr_gray_reg = {ADDR_WIDTH+1{1'b0}};
-reg [ADDR_WIDTH:0] rd_ptr_gray_reg = {ADDR_WIDTH+1{1'b0}}, rd_ptr_gray_next;
-reg [ADDR_WIDTH:0] rd_addr_reg = {ADDR_WIDTH+1{1'b0}};
 
+reg [ADDR_WIDTH:0] wr_ptr_temp;
+reg [ADDR_WIDTH:0] rd_ptr_temp;
+
+(* SHREG_EXTRACT = "NO" *)
 reg [ADDR_WIDTH:0] wr_ptr_gray_sync1_reg = {ADDR_WIDTH+1{1'b0}};
+(* SHREG_EXTRACT = "NO" *)
 reg [ADDR_WIDTH:0] wr_ptr_gray_sync2_reg = {ADDR_WIDTH+1{1'b0}};
+(* SHREG_EXTRACT = "NO" *)
 reg [ADDR_WIDTH:0] rd_ptr_gray_sync1_reg = {ADDR_WIDTH+1{1'b0}};
+(* SHREG_EXTRACT = "NO" *)
 reg [ADDR_WIDTH:0] rd_ptr_gray_sync2_reg = {ADDR_WIDTH+1{1'b0}};
 
-reg wr_ptr_update_valid_reg = 1'b0, wr_ptr_update_valid_next;
+reg wr_ptr_update_valid_reg = 1'b0;
-reg wr_ptr_update_reg = 1'b0, wr_ptr_update_next;
+reg wr_ptr_update_reg = 1'b0;
+(* SHREG_EXTRACT = "NO" *)
 reg wr_ptr_update_sync1_reg = 1'b0;
+(* SHREG_EXTRACT = "NO" *)
 reg wr_ptr_update_sync2_reg = 1'b0;
+(* SHREG_EXTRACT = "NO" *)
 reg wr_ptr_update_sync3_reg = 1'b0;
+(* SHREG_EXTRACT = "NO" *)
 reg wr_ptr_update_ack_sync1_reg = 1'b0;
+(* SHREG_EXTRACT = "NO" *)
 reg wr_ptr_update_ack_sync2_reg = 1'b0;
 
+(* SHREG_EXTRACT = "NO" *)
 reg s_rst_sync1_reg = 1'b1;
+(* SHREG_EXTRACT = "NO" *)
 reg s_rst_sync2_reg = 1'b1;
+(* SHREG_EXTRACT = "NO" *)
 reg s_rst_sync3_reg = 1'b1;
+(* SHREG_EXTRACT = "NO" *)
 reg m_rst_sync1_reg = 1'b1;
+(* SHREG_EXTRACT = "NO" *)
 reg m_rst_sync2_reg = 1'b1;
+(* SHREG_EXTRACT = "NO" *)
 reg m_rst_sync3_reg = 1'b1;
 
 reg [WIDTH-1:0] mem[(2**ADDR_WIDTH)-1:0];
 reg [WIDTH-1:0] mem_read_data_reg;
-reg mem_read_data_valid_reg = 1'b0, mem_read_data_valid_next;
+reg mem_read_data_valid_reg = 1'b0;
 
 wire [WIDTH-1:0] s_axis;
 
-reg [WIDTH-1:0] m_axis_reg;
+(* SHREG_EXTRACT = "NO" *)
-reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
+reg [WIDTH-1:0] m_axis_pipe_reg[PIPELINE_OUTPUT-1:0];
+(* SHREG_EXTRACT = "NO" *)
+reg [PIPELINE_OUTPUT-1:0] m_axis_tvalid_pipe_reg = 1'b0;
 
 // full when first TWO MSBs do NOT match, but rest matches
 // (gray code equivalent of first MSB different but rest same)
-wire full = ((wr_ptr_gray_reg[ADDR_WIDTH] != rd_ptr_gray_sync2_reg[ADDR_WIDTH]) &&
+wire full = wr_ptr_gray_reg == (rd_ptr_gray_sync2_reg ^ {2'b11, {ADDR_WIDTH-1{1'b0}}});
-             (wr_ptr_gray_reg[ADDR_WIDTH-1] != rd_ptr_gray_sync2_reg[ADDR_WIDTH-1]) &&
+wire full_cur = wr_ptr_cur_gray_reg == (rd_ptr_gray_sync2_reg ^ {2'b11, {ADDR_WIDTH-1{1'b0}}});
-             (wr_ptr_gray_reg[ADDR_WIDTH-2:0] == rd_ptr_gray_sync2_reg[ADDR_WIDTH-2:0]));
-wire full_cur = ((wr_ptr_cur_gray_reg[ADDR_WIDTH] != rd_ptr_gray_sync2_reg[ADDR_WIDTH]) &&
-                 (wr_ptr_cur_gray_reg[ADDR_WIDTH-1] != rd_ptr_gray_sync2_reg[ADDR_WIDTH-1]) &&
-                 (wr_ptr_cur_gray_reg[ADDR_WIDTH-2:0] == rd_ptr_gray_sync2_reg[ADDR_WIDTH-2:0]));
 // empty when pointers match exactly
 wire empty = rd_ptr_gray_reg == (FRAME_FIFO ? wr_ptr_gray_sync1_reg : wr_ptr_gray_sync2_reg);
 // overflow within packet
-wire full_wr = ((wr_ptr_reg[ADDR_WIDTH] != wr_ptr_cur_reg[ADDR_WIDTH]) &&
+wire full_wr = wr_ptr_reg == (wr_ptr_cur_reg ^ {1'b1, {ADDR_WIDTH{1'b0}}});
-                (wr_ptr_reg[ADDR_WIDTH-1:0] == wr_ptr_cur_reg[ADDR_WIDTH-1:0]));
 
 // control signals
 reg write;
 reg read;
 reg store_output;
 
-reg drop_frame_reg = 1'b0, drop_frame_next;
+reg drop_frame_reg = 1'b0;
-reg overflow_reg = 1'b0, overflow_next;
+reg overflow_reg = 1'b0;
-reg bad_frame_reg = 1'b0, bad_frame_next;
+reg bad_frame_reg = 1'b0;
-reg good_frame_reg = 1'b0, good_frame_next;
+reg good_frame_reg = 1'b0;
 
 reg overflow_sync1_reg = 1'b0;
 reg overflow_sync2_reg = 1'b0;
@@ -234,14 +254,14 @@ generate
     if (USER_ENABLE) assign s_axis[USER_OFFSET +: USER_WIDTH] = s_axis_tuser;
 endgenerate
 
-assign m_axis_tvalid = m_axis_tvalid_reg;
+assign m_axis_tvalid = m_axis_tvalid_pipe_reg[PIPELINE_OUTPUT-1];
 
-assign m_axis_tdata = m_axis_reg[DATA_WIDTH-1:0];
+assign m_axis_tdata = m_axis_pipe_reg[PIPELINE_OUTPUT-1][DATA_WIDTH-1:0];
-assign m_axis_tkeep = KEEP_ENABLE ? m_axis_reg[KEEP_OFFSET +: KEEP_WIDTH] : {KEEP_WIDTH{1'b1}};
+assign m_axis_tkeep = KEEP_ENABLE ? m_axis_pipe_reg[PIPELINE_OUTPUT-1][KEEP_OFFSET +: KEEP_WIDTH] : {KEEP_WIDTH{1'b1}};
-assign m_axis_tlast = LAST_ENABLE ? m_axis_reg[LAST_OFFSET]               : 1'b1;
+assign m_axis_tlast = LAST_ENABLE ? m_axis_pipe_reg[PIPELINE_OUTPUT-1][LAST_OFFSET]               : 1'b1;
-assign m_axis_tid   = ID_ENABLE   ? m_axis_reg[ID_OFFSET   +: ID_WIDTH]   : {ID_WIDTH{1'b0}};
+assign m_axis_tid   = ID_ENABLE   ? m_axis_pipe_reg[PIPELINE_OUTPUT-1][ID_OFFSET   +: ID_WIDTH]   : {ID_WIDTH{1'b0}};
-assign m_axis_tdest = DEST_ENABLE ? m_axis_reg[DEST_OFFSET +: DEST_WIDTH] : {DEST_WIDTH{1'b0}};
+assign m_axis_tdest = DEST_ENABLE ? m_axis_pipe_reg[PIPELINE_OUTPUT-1][DEST_OFFSET +: DEST_WIDTH] : {DEST_WIDTH{1'b0}};
-assign m_axis_tuser = USER_ENABLE ? m_axis_reg[USER_OFFSET +: USER_WIDTH] : {USER_WIDTH{1'b0}};
+assign m_axis_tuser = USER_ENABLE ? m_axis_pipe_reg[PIPELINE_OUTPUT-1][USER_OFFSET +: USER_WIDTH] : {USER_WIDTH{1'b0}};
 
 assign s_status_overflow = overflow_reg;
 assign s_status_bad_frame = bad_frame_reg;
@@ -277,30 +297,18 @@ always @(posedge m_clk or posedge async_rst) begin
 end
 
 // Write logic
-always @* begin
+always @(posedge s_clk) begin
-    write = 1'b0;
+    overflow_reg <= 1'b0;
-
+    bad_frame_reg <= 1'b0;
-    drop_frame_next = drop_frame_reg;
+    good_frame_reg <= 1'b0;
-    overflow_next = 1'b0;
-    bad_frame_next = 1'b0;
-    good_frame_next = 1'b0;
-
-    wr_ptr_next = wr_ptr_reg;
-    wr_ptr_cur_next = wr_ptr_cur_reg;
-    wr_ptr_gray_next = wr_ptr_gray_reg;
-    wr_ptr_sync_gray_next = wr_ptr_sync_gray_reg;
-    wr_ptr_cur_gray_next = wr_ptr_cur_gray_reg;
-
-    wr_ptr_update_valid_next = wr_ptr_update_valid_reg;
-    wr_ptr_update_next = wr_ptr_update_reg;
 
     if (FRAME_FIFO && wr_ptr_update_valid_reg) begin
         // have updated pointer to sync
-        if (wr_ptr_update_next == wr_ptr_update_ack_sync2_reg) begin
+        if (wr_ptr_update_reg == wr_ptr_update_ack_sync2_reg) begin
             // no sync in progress; sync update
-            wr_ptr_update_valid_next = 1'b0;
+            wr_ptr_update_valid_reg <= 1'b0;
-            wr_ptr_sync_gray_next = wr_ptr_gray_reg;
+            wr_ptr_sync_gray_reg <= wr_ptr_gray_reg;
-            wr_ptr_update_next = !wr_ptr_update_ack_sync2_reg;
+            wr_ptr_update_reg <= !wr_ptr_update_ack_sync2_reg;
         end
     end
 
@@ -308,54 +316,57 @@ always @* begin
         // transfer in
         if (!FRAME_FIFO) begin
             // normal FIFO mode
-            write = 1'b1;
+            mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis;
-            wr_ptr_next = wr_ptr_reg + 1;
+            wr_ptr_temp = wr_ptr_reg + 1;
-            wr_ptr_gray_next = wr_ptr_next ^ (wr_ptr_next >> 1);
+            wr_ptr_reg <= wr_ptr_temp;
+            wr_ptr_gray_reg <= wr_ptr_temp ^ (wr_ptr_temp >> 1);
         end else if (full_cur || full_wr || drop_frame_reg) begin
             // full, packet overflow, or currently dropping frame
             // drop frame
-            drop_frame_next = 1'b1;
+            drop_frame_reg <= 1'b1;
             if (s_axis_tlast) begin
                 // end of frame, reset write pointer
-                wr_ptr_cur_next = wr_ptr_reg;
+                wr_ptr_temp = wr_ptr_reg;
-                wr_ptr_cur_gray_next = wr_ptr_cur_next ^ (wr_ptr_cur_next >> 1);
+                wr_ptr_cur_reg <= wr_ptr_temp;
-                drop_frame_next = 1'b0;
+                wr_ptr_cur_gray_reg <= wr_ptr_temp ^ (wr_ptr_temp >> 1);
-                overflow_next = 1'b1;
+                drop_frame_reg <= 1'b0;
+                overflow_reg <= 1'b1;
             end
         end else begin
-            write = 1'b1;
+            mem[wr_ptr_cur_reg[ADDR_WIDTH-1:0]] <= s_axis;
-            wr_ptr_cur_next = wr_ptr_cur_reg + 1;
+            wr_ptr_temp = wr_ptr_cur_reg + 1;
-            wr_ptr_cur_gray_next = wr_ptr_cur_next ^ (wr_ptr_cur_next >> 1);
+            wr_ptr_cur_reg <= wr_ptr_temp;
+            wr_ptr_cur_gray_reg <= wr_ptr_temp ^ (wr_ptr_temp >> 1);
             if (s_axis_tlast) begin
                 // end of frame
                 if (DROP_BAD_FRAME && USER_BAD_FRAME_MASK & ~(s_axis_tuser ^ USER_BAD_FRAME_VALUE)) begin
                     // bad packet, reset write pointer
-                    wr_ptr_cur_next = wr_ptr_reg;
+                    wr_ptr_temp = wr_ptr_reg;
-                    wr_ptr_cur_gray_next = wr_ptr_cur_next ^ (wr_ptr_cur_next >> 1);
+                    wr_ptr_cur_reg <= wr_ptr_temp;
-                    bad_frame_next = 1'b1;
+                    wr_ptr_cur_gray_reg <= wr_ptr_temp ^ (wr_ptr_temp >> 1);
+                    bad_frame_reg <= 1'b1;
                 end else begin
                     // good packet, update write pointer
-                    wr_ptr_next = wr_ptr_cur_reg + 1;
+                    wr_ptr_temp = wr_ptr_cur_reg + 1;
-                    wr_ptr_gray_next = wr_ptr_next ^ (wr_ptr_next >> 1);
+                    wr_ptr_reg <= wr_ptr_temp;
+                    wr_ptr_gray_reg <= wr_ptr_temp ^ (wr_ptr_temp >> 1);
 
-                    if (wr_ptr_update_next == wr_ptr_update_ack_sync2_reg) begin
+                    if (wr_ptr_update_reg == wr_ptr_update_ack_sync2_reg) begin
                         // no sync in progress; sync update
-                        wr_ptr_update_valid_next = 1'b0;
+                        wr_ptr_update_valid_reg <= 1'b0;
-                        wr_ptr_sync_gray_next = wr_ptr_gray_next;
+                        wr_ptr_sync_gray_reg <= wr_ptr_temp ^ (wr_ptr_temp >> 1);
-                        wr_ptr_update_next = !wr_ptr_update_ack_sync2_reg;
+                        wr_ptr_update_reg <= !wr_ptr_update_ack_sync2_reg;
                     end else begin
                         // sync in progress; flag it for later
-                        wr_ptr_update_valid_next = 1'b1;
+                        wr_ptr_update_valid_reg <= 1'b1;
                     end
 
-                    good_frame_next = 1'b1;
+                    good_frame_reg <= 1'b1;
                 end
             end
         end
     end
-end
 
-always @(posedge s_clk) begin
     if (s_rst_sync3_reg) begin
         wr_ptr_reg <= {ADDR_WIDTH+1{1'b0}};
         wr_ptr_cur_reg <= {ADDR_WIDTH+1{1'b0}};
@@ -370,56 +381,25 @@ always @(posedge s_clk) begin
         overflow_reg <= 1'b0;
         bad_frame_reg <= 1'b0;
         good_frame_reg <= 1'b0;
-    end else begin
-        wr_ptr_reg <= wr_ptr_next;
-        wr_ptr_cur_reg <= wr_ptr_cur_next;
-        wr_ptr_gray_reg <= wr_ptr_gray_next;
-        wr_ptr_sync_gray_reg <= wr_ptr_sync_gray_next;
-        wr_ptr_cur_gray_reg <= wr_ptr_cur_gray_next;
-
-        wr_ptr_update_valid_reg <= wr_ptr_update_valid_next;
-        wr_ptr_update_reg <= wr_ptr_update_next;
-
-        drop_frame_reg <= drop_frame_next;
-        overflow_reg <= overflow_next;
-        bad_frame_reg <= bad_frame_next;
-        good_frame_reg <= good_frame_next;
-    end
-
-    if (FRAME_FIFO) begin
-        wr_addr_reg <= wr_ptr_cur_next;
-    end else begin
-        wr_addr_reg <= wr_ptr_next;
-    end
-
-    if (write) begin
-        mem[wr_addr_reg[ADDR_WIDTH-1:0]] <= s_axis;
     end
 end
 
 // pointer synchronization
 always @(posedge s_clk) begin
+    rd_ptr_gray_sync1_reg <= rd_ptr_gray_reg;
+    rd_ptr_gray_sync2_reg <= rd_ptr_gray_sync1_reg;
+    wr_ptr_update_ack_sync1_reg <= wr_ptr_update_sync3_reg;
+    wr_ptr_update_ack_sync2_reg <= wr_ptr_update_ack_sync1_reg;
+
     if (s_rst_sync3_reg) begin
         rd_ptr_gray_sync1_reg <= {ADDR_WIDTH+1{1'b0}};
         rd_ptr_gray_sync2_reg <= {ADDR_WIDTH+1{1'b0}};
         wr_ptr_update_ack_sync1_reg <= 1'b0;
         wr_ptr_update_ack_sync2_reg <= 1'b0;
-    end else begin
-        rd_ptr_gray_sync1_reg <= rd_ptr_gray_reg;
-        rd_ptr_gray_sync2_reg <= rd_ptr_gray_sync1_reg;
-        wr_ptr_update_ack_sync1_reg <= wr_ptr_update_sync3_reg;
-        wr_ptr_update_ack_sync2_reg <= wr_ptr_update_ack_sync1_reg;
     end
 end
 
 always @(posedge m_clk) begin
-    if (m_rst_sync3_reg) begin
-        wr_ptr_gray_sync1_reg <= {ADDR_WIDTH+1{1'b0}};
-        wr_ptr_gray_sync2_reg <= {ADDR_WIDTH+1{1'b0}};
-        wr_ptr_update_sync1_reg <= 1'b0;
-        wr_ptr_update_sync2_reg <= 1'b0;
-        wr_ptr_update_sync3_reg <= 1'b0;
-    end else begin
     if (!FRAME_FIFO) begin
         wr_ptr_gray_sync1_reg <= wr_ptr_gray_reg;
     end else if (wr_ptr_update_sync2_reg ^ wr_ptr_update_sync3_reg) begin
@@ -429,23 +409,40 @@ always @(posedge m_clk) begin
     wr_ptr_update_sync1_reg <= wr_ptr_update_reg;
     wr_ptr_update_sync2_reg <= wr_ptr_update_sync1_reg;
     wr_ptr_update_sync3_reg <= wr_ptr_update_sync2_reg;
+
+    if (m_rst_sync3_reg) begin
+        wr_ptr_gray_sync1_reg <= {ADDR_WIDTH+1{1'b0}};
+        wr_ptr_gray_sync2_reg <= {ADDR_WIDTH+1{1'b0}};
+        wr_ptr_update_sync1_reg <= 1'b0;
+        wr_ptr_update_sync2_reg <= 1'b0;
+        wr_ptr_update_sync3_reg <= 1'b0;
     end
 end
 
 // status synchronization
 always @(posedge s_clk) begin
+    overflow_sync1_reg <= overflow_sync1_reg ^ overflow_reg;
+    bad_frame_sync1_reg <= bad_frame_sync1_reg ^ bad_frame_reg;
+    good_frame_sync1_reg <= good_frame_sync1_reg ^ good_frame_reg;
+
     if (s_rst_sync3_reg) begin
         overflow_sync1_reg <= 1'b0;
         bad_frame_sync1_reg <= 1'b0;
         good_frame_sync1_reg <= 1'b0;
-    end else begin
-        overflow_sync1_reg <= overflow_sync1_reg ^ overflow_reg;
-        bad_frame_sync1_reg <= bad_frame_sync1_reg ^ bad_frame_reg;
-        good_frame_sync1_reg <= good_frame_sync1_reg ^ good_frame_reg;
     end
 end
 
 always @(posedge m_clk) begin
+    overflow_sync2_reg <= overflow_sync1_reg;
+    overflow_sync3_reg <= overflow_sync2_reg;
+    overflow_sync4_reg <= overflow_sync3_reg;
+    bad_frame_sync2_reg <= bad_frame_sync1_reg;
+    bad_frame_sync3_reg <= bad_frame_sync2_reg;
+    bad_frame_sync4_reg <= bad_frame_sync3_reg;
+    good_frame_sync2_reg <= good_frame_sync1_reg;
+    good_frame_sync3_reg <= good_frame_sync2_reg;
+    good_frame_sync4_reg <= good_frame_sync3_reg;
+
     if (m_rst_sync3_reg) begin
         overflow_sync2_reg <= 1'b0;
         overflow_sync3_reg <= 1'b0;
@@ -456,82 +453,44 @@ always @(posedge m_clk) begin
         good_frame_sync2_reg <= 1'b0;
         good_frame_sync3_reg <= 1'b0;
         good_frame_sync4_reg <= 1'b0;
-    end else begin
-        overflow_sync2_reg <= overflow_sync1_reg;
-        overflow_sync3_reg <= overflow_sync2_reg;
-        overflow_sync4_reg <= overflow_sync3_reg;
-        bad_frame_sync2_reg <= bad_frame_sync1_reg;
-        bad_frame_sync3_reg <= bad_frame_sync2_reg;
-        bad_frame_sync4_reg <= bad_frame_sync3_reg;
-        good_frame_sync2_reg <= good_frame_sync1_reg;
-        good_frame_sync3_reg <= good_frame_sync2_reg;
-        good_frame_sync4_reg <= good_frame_sync3_reg;
     end
 end
 
 // Read logic
-always @* begin
+integer j;
-    read = 1'b0;
-
-    rd_ptr_next = rd_ptr_reg;
-    rd_ptr_gray_next = rd_ptr_gray_reg;
-
-    mem_read_data_valid_next = mem_read_data_valid_reg;
-
-    if (store_output || !mem_read_data_valid_reg) begin
-        // output data not valid OR currently being transferred
-        if (!empty) begin
-            // not empty, perform read
-            read = 1'b1;
-            mem_read_data_valid_next = 1'b1;
-            rd_ptr_next = rd_ptr_reg + 1;
-            rd_ptr_gray_next = rd_ptr_next ^ (rd_ptr_next >> 1);
-        end else begin
-            // empty, invalidate
-            mem_read_data_valid_next = 1'b0;
-        end
-    end
-end
 
 always @(posedge m_clk) begin
+    if (m_axis_tready) begin
+        // output ready; invalidate stage
+        m_axis_tvalid_pipe_reg[PIPELINE_OUTPUT-1] <= 1'b0;
+    end
+
+    for (j = PIPELINE_OUTPUT-1; j > 0; j = j - 1) begin
+        if (m_axis_tready || ((~m_axis_tvalid_pipe_reg) >> j)) begin
+            // output ready or bubble in pipeline; transfer down pipeline
+            m_axis_tvalid_pipe_reg[j] <= m_axis_tvalid_pipe_reg[j-1];
+            m_axis_pipe_reg[j] <= m_axis_pipe_reg[j-1];
+            m_axis_tvalid_pipe_reg[j-1] <= 1'b0;
+        end
+    end
+
+    if (m_axis_tready || ~m_axis_tvalid_pipe_reg) begin
+        // output ready or bubble in pipeline; read new data from FIFO
+        m_axis_tvalid_pipe_reg[0] <= 1'b0;
+        m_axis_pipe_reg[0] <= mem[rd_ptr_reg[ADDR_WIDTH-1:0]];
+        if (!empty) begin
+            // not empty, increment pointer
+            m_axis_tvalid_pipe_reg[0] <= 1'b1;
+            rd_ptr_temp = rd_ptr_reg + 1;
+            rd_ptr_reg <= rd_ptr_temp;
+            rd_ptr_gray_reg <= rd_ptr_temp ^ (rd_ptr_temp >> 1);
+        end
+    end
+
     if (m_rst_sync3_reg) begin
         rd_ptr_reg <= {ADDR_WIDTH+1{1'b0}};
         rd_ptr_gray_reg <= {ADDR_WIDTH+1{1'b0}};
-        mem_read_data_valid_reg <= 1'b0;
+        m_axis_tvalid_pipe_reg <= {PIPELINE_OUTPUT{1'b0}};
-    end else begin
-        rd_ptr_reg <= rd_ptr_next;
-        rd_ptr_gray_reg <= rd_ptr_gray_next;
-        mem_read_data_valid_reg <= mem_read_data_valid_next;
-    end
-
-    rd_addr_reg <= rd_ptr_next;
-
-    if (read) begin
-        mem_read_data_reg <= mem[rd_addr_reg[ADDR_WIDTH-1:0]];
-    end
-end
-
-// Output register
-always @* begin
-    store_output = 1'b0;
-
-    m_axis_tvalid_next = m_axis_tvalid_reg;
-
-    if (m_axis_tready || !m_axis_tvalid) begin
-        store_output = 1'b1;
-        m_axis_tvalid_next = mem_read_data_valid_reg;
-    end
-end
-
-always @(posedge m_clk) begin
-    if (m_rst_sync3_reg) begin
-        m_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_axis_tvalid_reg <= m_axis_tvalid_next;
-    end
-
-    if (store_output) begin
-        m_axis_reg <= mem_read_data_reg;
     end
 end
 

fpga/lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v

@@ -61,6 +61,8 @@ module axis_async_fifo_adapter #
     parameter USER_ENABLE = 1,
     // tuser signal width
     parameter USER_WIDTH = 1,
+    // number of output pipeline registers
+    parameter PIPELINE_OUTPUT = 2,
     // Frame FIFO mode - operate on frames instead of cycles
     // When set, m_axis_tvalid will not be deasserted within a frame
     // Requires LAST_ENABLE set
@@ -307,6 +309,7 @@ axis_async_fifo #(
     .DEST_WIDTH(DEST_WIDTH),
     .USER_ENABLE(USER_ENABLE),
     .USER_WIDTH(USER_WIDTH),
+    .PIPELINE_OUTPUT(PIPELINE_OUTPUT),
     .FRAME_FIFO(FRAME_FIFO),
     .USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
     .USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),

fpga/lib/eth/lib/axis/rtl/axis_fifo.v

@@ -56,6 +56,8 @@ module axis_fifo #
     parameter USER_ENABLE = 1,
     // tuser signal width
     parameter USER_WIDTH = 1,
+    // number of output pipeline registers
+    parameter PIPELINE_OUTPUT = 2,
     // Frame FIFO mode - operate on frames instead of cycles
     // When set, m_axis_tvalid will not be deasserted within a frame
     // Requires LAST_ENABLE set
@@ -112,6 +114,11 @@ parameter ADDR_WIDTH = (KEEP_ENABLE && KEEP_WIDTH > 1) ? $clog2(DEPTH/KEEP_WIDTH
 
 // check configuration
 initial begin
+    if (PIPELINE_OUTPUT < 1) begin
+        $error("Error: PIPELINE_OUTPUT must be at least 1 (instance %m)");
+        $finish;
+    end
+
     if (FRAME_FIFO && !LAST_ENABLE) begin
         $error("Error: FRAME_FIFO set requires LAST_ENABLE set (instance %m)");
         $finish;
@@ -140,41 +147,31 @@ localparam DEST_OFFSET = ID_OFFSET   + (ID_ENABLE   ? ID_WIDTH   : 0);
 localparam USER_OFFSET = DEST_OFFSET + (DEST_ENABLE ? DEST_WIDTH : 0);
 localparam WIDTH       = USER_OFFSET + (USER_ENABLE ? USER_WIDTH : 0);
 
-reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_next;
+reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}};
-reg [ADDR_WIDTH:0] wr_ptr_cur_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_cur_next;
+reg [ADDR_WIDTH:0] wr_ptr_cur_reg = {ADDR_WIDTH+1{1'b0}};
-reg [ADDR_WIDTH:0] wr_addr_reg = {ADDR_WIDTH+1{1'b0}};
+reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}};
-reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}}, rd_ptr_next;
-reg [ADDR_WIDTH:0] rd_addr_reg = {ADDR_WIDTH+1{1'b0}};
 
 reg [WIDTH-1:0] mem[(2**ADDR_WIDTH)-1:0];
 reg [WIDTH-1:0] mem_read_data_reg;
-reg mem_read_data_valid_reg = 1'b0, mem_read_data_valid_next;
+reg mem_read_data_valid_reg = 1'b0;
 
 wire [WIDTH-1:0] s_axis;
 
-reg [WIDTH-1:0] m_axis_reg;
+reg [WIDTH-1:0] m_axis_pipe_reg[PIPELINE_OUTPUT-1:0];
-reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
+reg [PIPELINE_OUTPUT-1:0] m_axis_tvalid_pipe_reg = 1'b0;
 
 // full when first MSB different but rest same
-wire full = ((wr_ptr_reg[ADDR_WIDTH] != rd_ptr_reg[ADDR_WIDTH]) &&
+wire full = wr_ptr_reg == (rd_ptr_reg ^ {1'b1, {ADDR_WIDTH{1'b0}}});
-             (wr_ptr_reg[ADDR_WIDTH-1:0] == rd_ptr_reg[ADDR_WIDTH-1:0]));
+wire full_cur = wr_ptr_cur_reg == (rd_ptr_reg ^ {1'b1, {ADDR_WIDTH{1'b0}}});
-wire full_cur = ((wr_ptr_cur_reg[ADDR_WIDTH] != rd_ptr_reg[ADDR_WIDTH]) &&
-                 (wr_ptr_cur_reg[ADDR_WIDTH-1:0] == rd_ptr_reg[ADDR_WIDTH-1:0]));
 // empty when pointers match exactly
 wire empty = wr_ptr_reg == rd_ptr_reg;
 // overflow within packet
-wire full_wr = ((wr_ptr_reg[ADDR_WIDTH] != wr_ptr_cur_reg[ADDR_WIDTH]) &&
+wire full_wr = wr_ptr_reg == (wr_ptr_cur_reg ^ {1'b1, {ADDR_WIDTH{1'b0}}});
-                (wr_ptr_reg[ADDR_WIDTH-1:0] == wr_ptr_cur_reg[ADDR_WIDTH-1:0]));
 
-// control signals
+reg drop_frame_reg = 1'b0;
-reg write;
+reg overflow_reg = 1'b0;
-reg read;
+reg bad_frame_reg = 1'b0;
-reg store_output;
+reg good_frame_reg = 1'b0;
-
-reg drop_frame_reg = 1'b0, drop_frame_next;
-reg overflow_reg = 1'b0, overflow_next;
-reg bad_frame_reg = 1'b0, bad_frame_next;
-reg good_frame_reg = 1'b0, good_frame_next;
 
 assign s_axis_tready = FRAME_FIFO ? (!full_cur || full_wr || DROP_WHEN_FULL) : !full;
 
@@ -187,67 +184,59 @@ generate
     if (USER_ENABLE) assign s_axis[USER_OFFSET +: USER_WIDTH] = s_axis_tuser;
 endgenerate
 
-assign m_axis_tvalid = m_axis_tvalid_reg;
+assign m_axis_tvalid = m_axis_tvalid_pipe_reg[PIPELINE_OUTPUT-1];
 
-assign m_axis_tdata = m_axis_reg[DATA_WIDTH-1:0];
+assign m_axis_tdata = m_axis_pipe_reg[PIPELINE_OUTPUT-1][DATA_WIDTH-1:0];
-assign m_axis_tkeep = KEEP_ENABLE ? m_axis_reg[KEEP_OFFSET +: KEEP_WIDTH] : {KEEP_WIDTH{1'b1}};
+assign m_axis_tkeep = KEEP_ENABLE ? m_axis_pipe_reg[PIPELINE_OUTPUT-1][KEEP_OFFSET +: KEEP_WIDTH] : {KEEP_WIDTH{1'b1}};
-assign m_axis_tlast = LAST_ENABLE ? m_axis_reg[LAST_OFFSET]               : 1'b1;
+assign m_axis_tlast = LAST_ENABLE ? m_axis_pipe_reg[PIPELINE_OUTPUT-1][LAST_OFFSET]               : 1'b1;
-assign m_axis_tid   = ID_ENABLE   ? m_axis_reg[ID_OFFSET   +: ID_WIDTH]   : {ID_WIDTH{1'b0}};
+assign m_axis_tid   = ID_ENABLE   ? m_axis_pipe_reg[PIPELINE_OUTPUT-1][ID_OFFSET   +: ID_WIDTH]   : {ID_WIDTH{1'b0}};
-assign m_axis_tdest = DEST_ENABLE ? m_axis_reg[DEST_OFFSET +: DEST_WIDTH] : {DEST_WIDTH{1'b0}};
+assign m_axis_tdest = DEST_ENABLE ? m_axis_pipe_reg[PIPELINE_OUTPUT-1][DEST_OFFSET +: DEST_WIDTH] : {DEST_WIDTH{1'b0}};
-assign m_axis_tuser = USER_ENABLE ? m_axis_reg[USER_OFFSET +: USER_WIDTH] : {USER_WIDTH{1'b0}};
+assign m_axis_tuser = USER_ENABLE ? m_axis_pipe_reg[PIPELINE_OUTPUT-1][USER_OFFSET +: USER_WIDTH] : {USER_WIDTH{1'b0}};
 
 assign status_overflow = overflow_reg;
 assign status_bad_frame = bad_frame_reg;
 assign status_good_frame = good_frame_reg;
 
 // Write logic
-always @* begin
+always @(posedge clk) begin
-    write = 1'b0;
+    overflow_reg <= 1'b0;
-
+    bad_frame_reg <= 1'b0;
-    drop_frame_next = drop_frame_reg;
+    good_frame_reg <= 1'b0;
-    overflow_next = 1'b0;
-    bad_frame_next = 1'b0;
-    good_frame_next = 1'b0;
-
-    wr_ptr_next = wr_ptr_reg;
-    wr_ptr_cur_next = wr_ptr_cur_reg;
 
     if (s_axis_tready && s_axis_tvalid) begin
         // transfer in
         if (!FRAME_FIFO) begin
             // normal FIFO mode
-            write = 1'b1;
+            mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis;
-            wr_ptr_next = wr_ptr_reg + 1;
+            wr_ptr_reg <= wr_ptr_reg + 1;
         end else if (full_cur || full_wr || drop_frame_reg) begin
             // full, packet overflow, or currently dropping frame
             // drop frame
-            drop_frame_next = 1'b1;
+            drop_frame_reg <= 1'b1;
             if (s_axis_tlast) begin
                 // end of frame, reset write pointer
-                wr_ptr_cur_next = wr_ptr_reg;
+                wr_ptr_cur_reg <= wr_ptr_reg;
-                drop_frame_next = 1'b0;
+                drop_frame_reg <= 1'b0;
-                overflow_next = 1'b1;
+                overflow_reg <= 1'b1;
             end
         end else begin
-            write = 1'b1;
+            mem[wr_ptr_cur_reg[ADDR_WIDTH-1:0]] <= s_axis;
-            wr_ptr_cur_next = wr_ptr_cur_reg + 1;
+            wr_ptr_cur_reg <= wr_ptr_cur_reg + 1;
             if (s_axis_tlast) begin
                 // end of frame
                 if (DROP_BAD_FRAME && USER_BAD_FRAME_MASK & ~(s_axis_tuser ^ USER_BAD_FRAME_VALUE)) begin
                     // bad packet, reset write pointer
-                    wr_ptr_cur_next = wr_ptr_reg;
+                    wr_ptr_cur_reg <= wr_ptr_reg;
-                    bad_frame_next = 1'b1;
+                    bad_frame_reg <= 1'b1;
                 end else begin
                     // good packet, update write pointer
-                    wr_ptr_next = wr_ptr_cur_reg + 1;
+                    wr_ptr_reg <= wr_ptr_cur_reg + 1;
-                    good_frame_next = 1'b1;
+                    good_frame_reg <= 1'b1;
                 end
             end
         end
     end
-end
 
-always @(posedge clk) begin
     if (rst) begin
         wr_ptr_reg <= {ADDR_WIDTH+1{1'b0}};
         wr_ptr_cur_reg <= {ADDR_WIDTH+1{1'b0}};
@@ -256,86 +245,41 @@ always @(posedge clk) begin
         overflow_reg <= 1'b0;
         bad_frame_reg <= 1'b0;
         good_frame_reg <= 1'b0;
-    end else begin
-        wr_ptr_reg <= wr_ptr_next;
-        wr_ptr_cur_reg <= wr_ptr_cur_next;
-
-        drop_frame_reg <= drop_frame_next;
-        overflow_reg <= overflow_next;
-        bad_frame_reg <= bad_frame_next;
-        good_frame_reg <= good_frame_next;
-    end
-
-    if (FRAME_FIFO) begin
-        wr_addr_reg <= wr_ptr_cur_next;
-    end else begin
-        wr_addr_reg <= wr_ptr_next;
-    end
-
-    if (write) begin
-        mem[wr_addr_reg[ADDR_WIDTH-1:0]] <= s_axis;
     end
 end
 
 // Read logic
-always @* begin
+integer j;
-    read = 1'b0;
-
-    rd_ptr_next = rd_ptr_reg;
-
-    mem_read_data_valid_next = mem_read_data_valid_reg;
-
-    if (store_output || !mem_read_data_valid_reg) begin
-        // output data not valid OR currently being transferred
-        if (!empty) begin
-            // not empty, perform read
-            read = 1'b1;
-            mem_read_data_valid_next = 1'b1;
-            rd_ptr_next = rd_ptr_reg + 1;
-        end else begin
-            // empty, invalidate
-            mem_read_data_valid_next = 1'b0;
-        end
-    end
-end
 
 always @(posedge clk) begin
+    if (m_axis_tready) begin
+        // output ready; invalidate stage
+        m_axis_tvalid_pipe_reg[PIPELINE_OUTPUT-1] <= 1'b0;
+    end
+
+    for (j = PIPELINE_OUTPUT-1; j > 0; j = j - 1) begin
+        if (m_axis_tready || ((~m_axis_tvalid_pipe_reg) >> j)) begin
+            // output ready or bubble in pipeline; transfer down pipeline
+            m_axis_tvalid_pipe_reg[j] <= m_axis_tvalid_pipe_reg[j-1];
+            m_axis_pipe_reg[j] <= m_axis_pipe_reg[j-1];
+            m_axis_tvalid_pipe_reg[j-1] <= 1'b0;
+        end
+    end
+
+    if (m_axis_tready || ~m_axis_tvalid_pipe_reg) begin
+        // output ready or bubble in pipeline; read new data from FIFO
+        m_axis_tvalid_pipe_reg[0] <= 1'b0;
+        m_axis_pipe_reg[0] <= mem[rd_ptr_reg[ADDR_WIDTH-1:0]];
+        if (!empty) begin
+            // not empty, increment pointer
+            m_axis_tvalid_pipe_reg[0] <= 1'b1;
+            rd_ptr_reg <= rd_ptr_reg + 1;
+        end
+    end
+
     if (rst) begin
         rd_ptr_reg <= {ADDR_WIDTH+1{1'b0}};
-        mem_read_data_valid_reg <= 1'b0;
+        m_axis_tvalid_pipe_reg <= {PIPELINE_OUTPUT{1'b0}};
-    end else begin
-        rd_ptr_reg <= rd_ptr_next;
-        mem_read_data_valid_reg <= mem_read_data_valid_next;
-    end
-
-    rd_addr_reg <= rd_ptr_next;
-
-    if (read) begin
-        mem_read_data_reg <= mem[rd_addr_reg[ADDR_WIDTH-1:0]];
-    end
-end
-
-// Output register
-always @* begin
-    store_output = 1'b0;
-
-    m_axis_tvalid_next = m_axis_tvalid_reg;
-
-    if (m_axis_tready || !m_axis_tvalid) begin
-        store_output = 1'b1;
-        m_axis_tvalid_next = mem_read_data_valid_reg;
-    end
-end
-
-always @(posedge clk) begin
-    if (rst) begin
-        m_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_axis_tvalid_reg <= m_axis_tvalid_next;
-    end
-
-    if (store_output) begin
-        m_axis_reg <= mem_read_data_reg;
     end
 end
 

fpga/lib/eth/lib/axis/rtl/axis_fifo_adapter.v

@@ -61,6 +61,8 @@ module axis_fifo_adapter #
     parameter USER_ENABLE = 1,
     // tuser signal width
     parameter USER_WIDTH = 1,
+    // number of output pipeline registers
+    parameter PIPELINE_OUTPUT = 2,
     // Frame FIFO mode - operate on frames instead of cycles
     // When set, m_axis_tvalid will not be deasserted within a frame
     // Requires LAST_ENABLE set
@@ -302,6 +304,7 @@ axis_fifo #(
     .DEST_WIDTH(DEST_WIDTH),
     .USER_ENABLE(USER_ENABLE),
     .USER_WIDTH(USER_WIDTH),
+    .PIPELINE_OUTPUT(PIPELINE_OUTPUT),
     .FRAME_FIFO(FRAME_FIFO),
     .USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
     .USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),

fpga/lib/eth/lib/axis/rtl/axis_ram_switch.v

@@ -93,7 +93,9 @@ module axis_ram_switch #
     // arbitration type: "PRIORITY" or "ROUND_ROBIN"
     parameter ARB_TYPE = "ROUND_ROBIN",
     // LSB priority: "LOW", "HIGH"
-    parameter LSB_PRIORITY = "HIGH"
+    parameter LSB_PRIORITY = "HIGH",
+    // RAM read data output pipeline stages
+    parameter RAM_PIPELINE = 2
 )
 (
     input  wire                            clk,
@@ -217,8 +219,8 @@ end
 
 // Shared RAM
 reg [DATA_WIDTH-1:0] mem[(2**RAM_ADDR_WIDTH)-1:0];
-reg [DATA_WIDTH-1:0] mem_read_data_reg;
+reg [DATA_WIDTH-1:0] mem_read_data_reg[RAM_PIPELINE-1:0];
-reg [M_COUNT-1:0] mem_read_data_valid_reg;
+reg [M_COUNT-1:0] mem_read_data_valid_reg[RAM_PIPELINE-1:0];
 
 wire [S_COUNT*DATA_WIDTH-1:0]     port_ram_wr_data;
 wire [S_COUNT*RAM_ADDR_WIDTH-1:0] port_ram_wr_addr;
@@ -231,8 +233,8 @@ wire [M_COUNT-1:0]                port_ram_rd_ack;
 wire [M_COUNT*DATA_WIDTH-1:0]     port_ram_rd_data;
 wire [M_COUNT-1:0]                port_ram_rd_data_valid;
 
-assign port_ram_rd_data = {M_COUNT{mem_read_data_reg}};
+assign port_ram_rd_data = {M_COUNT{mem_read_data_reg[RAM_PIPELINE-1]}};
-assign port_ram_rd_data_valid = mem_read_data_valid_reg;
+assign port_ram_rd_data_valid = mem_read_data_valid_reg[RAM_PIPELINE-1];
 
 wire [CL_S_COUNT-1:0] ram_wr_sel;
 wire ram_wr_en;
@@ -306,16 +308,26 @@ end
 
 endgenerate
 
+integer s;
+
 always @(posedge clk) begin
-    mem_read_data_valid_reg <= 0;
+    mem_read_data_valid_reg[0] <= 0;
+
+    for (s = RAM_PIPELINE-1; s > 0; s = s - 1) begin
+        mem_read_data_reg[s] <= mem_read_data_reg[s-1];
+        mem_read_data_valid_reg[s] <= mem_read_data_valid_reg[s-1];
+    end
 
     if (ram_rd_en) begin
-        mem_read_data_reg <= mem[port_ram_rd_addr[ram_rd_sel*RAM_ADDR_WIDTH +: RAM_ADDR_WIDTH]];
+        mem_read_data_reg[0] <= mem[port_ram_rd_addr[ram_rd_sel*RAM_ADDR_WIDTH +: RAM_ADDR_WIDTH]];
-        mem_read_data_valid_reg <= 1 << ram_rd_sel;
+        mem_read_data_valid_reg[0] <= 1 << ram_rd_sel;
     end
 
     if (rst) begin
-        mem_read_data_valid_reg <= 0;
+        mem_read_data_valid_reg[0] <= 0;
+        for (s = 0; s < RAM_PIPELINE; s = s + 1) begin
+            mem_read_data_valid_reg[s] <= 0;
+        end
     end
 end
 

fpga/lib/eth/lib/axis/syn/axis_async_fifo.tcl

@@ -59,7 +59,7 @@ foreach fifo_inst [get_cells -hier -filter {(ORIG_REF_NAME == axis_async_fifo ||
     set_bus_skew  -from [get_cells -quiet "$fifo_inst/wr_ptr_reg_reg[*] $fifo_inst/wr_ptr_gray_reg_reg[*] $fifo_inst/wr_ptr_sync_gray_reg_reg[*]"] -to [get_cells $fifo_inst/wr_ptr_gray_sync1_reg_reg[*]] $read_clk_period
 
     # output register (needed for distributed RAM sync write/async read)
-    set output_reg_ffs [get_cells -quiet "$fifo_inst/mem_read_data_reg_reg[*]"]
+    set output_reg_ffs [get_cells -quiet "$fifo_inst/m_axis_pipe_reg_reg[0][*]"]
 
     if {[llength $output_reg_ffs]} {
         set_false_path -from $write_clk -to $output_reg_ffs

fpga/lib/eth/lib/axis/tb/test_axis_async_fifo.py

@@ -54,6 +54,7 @@ def bench():
     DEST_WIDTH = 8
     USER_ENABLE = 1
     USER_WIDTH = 1
+    PIPELINE_OUTPUT = 2
     FRAME_FIFO = 0
     USER_BAD_FRAME_VALUE = 1
     USER_BAD_FRAME_MASK = 1

fpga/lib/eth/lib/axis/tb/test_axis_async_fifo.v

@@ -43,6 +43,7 @@ parameter DEST_ENABLE = 1;
 parameter DEST_WIDTH = 8;
 parameter USER_ENABLE = 1;
 parameter USER_WIDTH = 1;
+parameter PIPELINE_OUTPUT = 2;
 parameter FRAME_FIFO = 0;
 parameter USER_BAD_FRAME_VALUE = 1'b1;
 parameter USER_BAD_FRAME_MASK = 1'b1;
@@ -118,6 +119,7 @@ axis_async_fifo #(
     .DEST_WIDTH(DEST_WIDTH),
     .USER_ENABLE(USER_ENABLE),
     .USER_WIDTH(USER_WIDTH),
+    .PIPELINE_OUTPUT(PIPELINE_OUTPUT),
     .FRAME_FIFO(FRAME_FIFO),
     .USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
     .USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),

fpga/lib/eth/lib/axis/tb/test_axis_async_fifo_64.py

@@ -54,6 +54,7 @@ def bench():
     DEST_WIDTH = 8
     USER_ENABLE = 1
     USER_WIDTH = 1
+    PIPELINE_OUTPUT = 2
     FRAME_FIFO = 0
     USER_BAD_FRAME_VALUE = 1
     USER_BAD_FRAME_MASK = 1

fpga/lib/eth/lib/axis/tb/test_axis_async_fifo_64.v

@@ -43,6 +43,7 @@ parameter DEST_ENABLE = 1;
 parameter DEST_WIDTH = 8;
 parameter USER_ENABLE = 1;
 parameter USER_WIDTH = 1;
+parameter PIPELINE_OUTPUT = 2;
 parameter FRAME_FIFO = 0;
 parameter USER_BAD_FRAME_VALUE = 1'b1;
 parameter USER_BAD_FRAME_MASK = 1'b1;
@@ -118,6 +119,7 @@ axis_async_fifo #(
     .DEST_WIDTH(DEST_WIDTH),
     .USER_ENABLE(USER_ENABLE),
     .USER_WIDTH(USER_WIDTH),
+    .PIPELINE_OUTPUT(PIPELINE_OUTPUT),
     .FRAME_FIFO(FRAME_FIFO),
     .USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
     .USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),

fpga/lib/eth/lib/axis/tb/test_axis_async_fifo_adapter_64_8.py

@@ -58,6 +58,7 @@ def bench():
     DEST_WIDTH = 8
     USER_ENABLE = 1
     USER_WIDTH = 1
+    PIPELINE_OUTPUT = 2
     FRAME_FIFO = 0
     USER_BAD_FRAME_VALUE = 1
     USER_BAD_FRAME_MASK = 1

fpga/lib/eth/lib/axis/tb/test_axis_async_fifo_adapter_64_8.v

@@ -45,6 +45,7 @@ parameter DEST_ENABLE = 1;
 parameter DEST_WIDTH = 8;
 parameter USER_ENABLE = 1;
 parameter USER_WIDTH = 1;
+parameter PIPELINE_OUTPUT = 2;
 parameter FRAME_FIFO = 0;
 parameter USER_BAD_FRAME_VALUE = 1'b1;
 parameter USER_BAD_FRAME_MASK = 1'b1;
@@ -124,6 +125,7 @@ axis_async_fifo_adapter #(
     .DEST_WIDTH(DEST_WIDTH),
     .USER_ENABLE(USER_ENABLE),
     .USER_WIDTH(USER_WIDTH),
+    .PIPELINE_OUTPUT(PIPELINE_OUTPUT),
     .FRAME_FIFO(FRAME_FIFO),
     .USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
     .USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),

fpga/lib/eth/lib/axis/tb/test_axis_async_fifo_adapter_8_64.py

@@ -58,6 +58,7 @@ def bench():
     DEST_WIDTH = 8
     USER_ENABLE = 1
     USER_WIDTH = 1
+    PIPELINE_OUTPUT = 2
     FRAME_FIFO = 0
     USER_BAD_FRAME_VALUE = 1
     USER_BAD_FRAME_MASK = 1

fpga/lib/eth/lib/axis/tb/test_axis_async_fifo_adapter_8_64.v

@@ -45,6 +45,7 @@ parameter DEST_ENABLE = 1;
 parameter DEST_WIDTH = 8;
 parameter USER_ENABLE = 1;
 parameter USER_WIDTH = 1;
+parameter PIPELINE_OUTPUT = 2;
 parameter FRAME_FIFO = 0;
 parameter USER_BAD_FRAME_VALUE = 1'b1;
 parameter USER_BAD_FRAME_MASK = 1'b1;
@@ -124,6 +125,7 @@ axis_async_fifo_adapter #(
     .DEST_WIDTH(DEST_WIDTH),
     .USER_ENABLE(USER_ENABLE),
     .USER_WIDTH(USER_WIDTH),
+    .PIPELINE_OUTPUT(PIPELINE_OUTPUT),
     .FRAME_FIFO(FRAME_FIFO),
     .USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
     .USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),

fpga/lib/eth/lib/axis/tb/test_axis_async_frame_fifo.py

@@ -54,6 +54,7 @@ def bench():
     DEST_WIDTH = 8
     USER_ENABLE = 1
     USER_WIDTH = 1
+    PIPELINE_OUTPUT = 2
     FRAME_FIFO = 1
     USER_BAD_FRAME_VALUE = 1
     USER_BAD_FRAME_MASK = 1

fpga/lib/eth/lib/axis/tb/test_axis_async_frame_fifo.v

@@ -43,6 +43,7 @@ parameter DEST_ENABLE = 1;
 parameter DEST_WIDTH = 8;
 parameter USER_ENABLE = 1;
 parameter USER_WIDTH = 1;
+parameter PIPELINE_OUTPUT = 2;
 parameter FRAME_FIFO = 1;
 parameter USER_BAD_FRAME_VALUE = 1'b1;
 parameter USER_BAD_FRAME_MASK = 1'b1;
@@ -130,6 +131,7 @@ axis_async_fifo #(
     .DEST_WIDTH(DEST_WIDTH),
     .USER_ENABLE(USER_ENABLE),
     .USER_WIDTH(USER_WIDTH),
+    .PIPELINE_OUTPUT(PIPELINE_OUTPUT),
     .FRAME_FIFO(FRAME_FIFO),
     .USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
     .USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),

fpga/lib/eth/lib/axis/tb/test_axis_async_frame_fifo_64.py

@@ -54,6 +54,7 @@ def bench():
     DEST_WIDTH = 8
     USER_ENABLE = 1
     USER_WIDTH = 1
+    PIPELINE_OUTPUT = 2;
     FRAME_FIFO = 1
     USER_BAD_FRAME_VALUE = 1
     USER_BAD_FRAME_MASK = 1

fpga/lib/eth/lib/axis/tb/test_axis_async_frame_fifo_64.v

@@ -43,6 +43,7 @@ parameter DEST_ENABLE = 1;
 parameter DEST_WIDTH = 8;
 parameter USER_ENABLE = 1;
 parameter USER_WIDTH = 1;
+parameter PIPELINE_OUTPUT = 2;
 parameter FRAME_FIFO = 1;
 parameter USER_BAD_FRAME_VALUE = 1'b1;
 parameter USER_BAD_FRAME_MASK = 1'b1;
@@ -130,6 +131,7 @@ axis_async_fifo #(
     .DEST_WIDTH(DEST_WIDTH),
     .USER_ENABLE(USER_ENABLE),
     .USER_WIDTH(USER_WIDTH),
+    .PIPELINE_OUTPUT(PIPELINE_OUTPUT),
     .FRAME_FIFO(FRAME_FIFO),
     .USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
     .USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),

fpga/lib/eth/lib/axis/tb/test_axis_fifo.py

@@ -54,6 +54,7 @@ def bench():
     DEST_WIDTH = 8
     USER_ENABLE = 1
     USER_WIDTH = 1
+    PIPELINE_OUTPUT = 2
     FRAME_FIFO = 0
     USER_BAD_FRAME_VALUE = 1
     USER_BAD_FRAME_MASK = 1

fpga/lib/eth/lib/axis/tb/test_axis_fifo.v

@@ -43,6 +43,7 @@ parameter DEST_ENABLE = 1;
 parameter DEST_WIDTH = 8;
 parameter USER_ENABLE = 1;
 parameter USER_WIDTH = 1;
+parameter PIPELINE_OUTPUT = 2;
 parameter FRAME_FIFO = 0;
 parameter USER_BAD_FRAME_VALUE = 1'b1;
 parameter USER_BAD_FRAME_MASK = 1'b1;
@@ -116,6 +117,7 @@ axis_fifo #(
     .DEST_WIDTH(DEST_WIDTH),
     .USER_ENABLE(USER_ENABLE),
     .USER_WIDTH(USER_WIDTH),
+    .PIPELINE_OUTPUT(PIPELINE_OUTPUT),
     .FRAME_FIFO(FRAME_FIFO),
     .USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
     .USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),

fpga/lib/eth/lib/axis/tb/test_axis_fifo_64.py

@@ -54,6 +54,7 @@ def bench():
     DEST_WIDTH = 8
     USER_ENABLE = 1
     USER_WIDTH = 1
+    PIPELINE_OUTPUT = 2
     FRAME_FIFO = 0
     USER_BAD_FRAME_VALUE = 1
     USER_BAD_FRAME_MASK = 1

fpga/lib/eth/lib/axis/tb/test_axis_fifo_64.v

@@ -43,6 +43,7 @@ parameter DEST_ENABLE = 1;
 parameter DEST_WIDTH = 8;
 parameter USER_ENABLE = 1;
 parameter USER_WIDTH = 1;
+parameter PIPELINE_OUTPUT = 2;
 parameter FRAME_FIFO = 0;
 parameter USER_BAD_FRAME_VALUE = 1'b1;
 parameter USER_BAD_FRAME_MASK = 1'b1;
@@ -116,6 +117,7 @@ axis_fifo #(
     .DEST_WIDTH(DEST_WIDTH),
     .USER_ENABLE(USER_ENABLE),
     .USER_WIDTH(USER_WIDTH),
+    .PIPELINE_OUTPUT(PIPELINE_OUTPUT),
     .FRAME_FIFO(FRAME_FIFO),
     .USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
     .USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),

fpga/lib/eth/lib/axis/tb/test_axis_fifo_adapter_64_8.py

@@ -58,6 +58,7 @@ def bench():
     DEST_WIDTH = 8
     USER_ENABLE = 1
     USER_WIDTH = 1
+    PIPELINE_OUTPUT = 2
     FRAME_FIFO = 0
     USER_BAD_FRAME_VALUE = 1
     USER_BAD_FRAME_MASK = 1

fpga/lib/eth/lib/axis/tb/test_axis_fifo_adapter_64_8.v

@@ -45,6 +45,7 @@ parameter DEST_ENABLE = 1;
 parameter DEST_WIDTH = 8;
 parameter USER_ENABLE = 1;
 parameter USER_WIDTH = 1;
+parameter PIPELINE_OUTPUT = 2;
 parameter FRAME_FIFO = 0;
 parameter USER_BAD_FRAME_VALUE = 1'b1;
 parameter USER_BAD_FRAME_MASK = 1'b1;
@@ -120,6 +121,7 @@ axis_fifo_adapter #(
     .DEST_WIDTH(DEST_WIDTH),
     .USER_ENABLE(USER_ENABLE),
     .USER_WIDTH(USER_WIDTH),
+    .PIPELINE_OUTPUT(PIPELINE_OUTPUT),
     .FRAME_FIFO(FRAME_FIFO),
     .USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
     .USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),

fpga/lib/eth/lib/axis/tb/test_axis_fifo_adapter_8_64.py

@@ -58,6 +58,7 @@ def bench():
     DEST_WIDTH = 8
     USER_ENABLE = 1
     USER_WIDTH = 1
+    PIPELINE_OUTPUT = 2
     FRAME_FIFO = 0
     USER_BAD_FRAME_VALUE = 1
     USER_BAD_FRAME_MASK = 1

fpga/lib/eth/lib/axis/tb/test_axis_fifo_adapter_8_64.v

@@ -45,6 +45,7 @@ parameter DEST_ENABLE = 1;
 parameter DEST_WIDTH = 8;
 parameter USER_ENABLE = 1;
 parameter USER_WIDTH = 1;
+parameter PIPELINE_OUTPUT = 2;
 parameter FRAME_FIFO = 0;
 parameter USER_BAD_FRAME_VALUE = 1'b1;
 parameter USER_BAD_FRAME_MASK = 1'b1;
@@ -120,6 +121,7 @@ axis_fifo_adapter #(
     .DEST_WIDTH(DEST_WIDTH),
     .USER_ENABLE(USER_ENABLE),
     .USER_WIDTH(USER_WIDTH),
+    .PIPELINE_OUTPUT(PIPELINE_OUTPUT),
     .FRAME_FIFO(FRAME_FIFO),
     .USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
     .USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),

fpga/lib/eth/lib/axis/tb/test_axis_frame_fifo.py

@@ -54,6 +54,7 @@ def bench():
     DEST_WIDTH = 8
     USER_ENABLE = 1
     USER_WIDTH = 1
+    PIPELINE_OUTPUT = 2
     FRAME_FIFO = 1
     USER_BAD_FRAME_VALUE = 1
     USER_BAD_FRAME_MASK = 1

fpga/lib/eth/lib/axis/tb/test_axis_frame_fifo.v

@@ -43,6 +43,7 @@ parameter DEST_ENABLE = 1;
 parameter DEST_WIDTH = 8;
 parameter USER_ENABLE = 1;
 parameter USER_WIDTH = 1;
+parameter PIPELINE_OUTPUT = 2;
 parameter FRAME_FIFO = 1;
 parameter USER_BAD_FRAME_VALUE = 1'b1;
 parameter USER_BAD_FRAME_MASK = 1'b1;
@@ -122,6 +123,7 @@ axis_fifo #(
     .DEST_WIDTH(DEST_WIDTH),
     .USER_ENABLE(USER_ENABLE),
     .USER_WIDTH(USER_WIDTH),
+    .PIPELINE_OUTPUT(PIPELINE_OUTPUT),
     .FRAME_FIFO(FRAME_FIFO),
     .USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
     .USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),

fpga/lib/eth/lib/axis/tb/test_axis_frame_fifo_64.py

@@ -54,6 +54,7 @@ def bench():
     DEST_WIDTH = 8
     USER_ENABLE = 1
     USER_WIDTH = 1
+    PIPELINE_OUTPUT = 2
     FRAME_FIFO = 1
     USER_BAD_FRAME_VALUE = 1
     USER_BAD_FRAME_MASK = 1

fpga/lib/eth/lib/axis/tb/test_axis_frame_fifo_64.v

@@ -43,6 +43,7 @@ parameter DEST_ENABLE = 1;
 parameter DEST_WIDTH = 8;
 parameter USER_ENABLE = 1;
 parameter USER_WIDTH = 1;
+parameter PIPELINE_OUTPUT = 2;
 parameter FRAME_FIFO = 1;
 parameter USER_BAD_FRAME_VALUE = 1'b1;
 parameter USER_BAD_FRAME_MASK = 1'b1;
@@ -122,6 +123,7 @@ axis_fifo #(
     .DEST_WIDTH(DEST_WIDTH),
     .USER_ENABLE(USER_ENABLE),
     .USER_WIDTH(USER_WIDTH),
+    .PIPELINE_OUTPUT(PIPELINE_OUTPUT),
     .FRAME_FIFO(FRAME_FIFO),
     .USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
     .USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),

fpga/lib/eth/lib/axis/tb/test_axis_ram_switch_1x4_256_64.py

@@ -72,6 +72,7 @@ def bench():
     M_CONNECT = [0b1111]*M_COUNT
     ARB_TYPE = "ROUND_ROBIN"
     LSB_PRIORITY = "HIGH"
+    RAM_PIPELINE = 2
 
     # Inputs
     clk = Signal(bool(0))

fpga/lib/eth/lib/axis/tb/test_axis_ram_switch_1x4_256_64.v

@@ -56,6 +56,7 @@ parameter M_TOP = {3'd3, 3'd2, 3'd1, 3'd0};
 parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}};
 parameter ARB_TYPE = "ROUND_ROBIN";
 parameter LSB_PRIORITY = "HIGH";
+parameter RAM_PIPELINE = 2;
 
 // Inputs
 reg clk = 0;
@@ -142,7 +143,8 @@ axis_ram_switch #(
     .M_TOP(M_TOP),
     .M_CONNECT(M_CONNECT),
     .ARB_TYPE(ARB_TYPE),
-    .LSB_PRIORITY(LSB_PRIORITY)
+    .LSB_PRIORITY(LSB_PRIORITY),
+    .RAM_PIPELINE(RAM_PIPELINE)
 )
 UUT (
     .clk(clk),

fpga/lib/eth/lib/axis/tb/test_axis_ram_switch_4x1_64_256.py

@@ -72,6 +72,7 @@ def bench():
     M_CONNECT = [0b1111]*M_COUNT
     ARB_TYPE = "ROUND_ROBIN"
     LSB_PRIORITY = "HIGH"
+    RAM_PIPELINE = 2
 
     # Inputs
     clk = Signal(bool(0))

fpga/lib/eth/lib/axis/tb/test_axis_ram_switch_4x1_64_256.v

@@ -56,6 +56,7 @@ parameter M_TOP = {3'd3, 3'd2, 3'd1, 3'd0};
 parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}};
 parameter ARB_TYPE = "ROUND_ROBIN";
 parameter LSB_PRIORITY = "HIGH";
+parameter RAM_PIPELINE = 2;
 
 // Inputs
 reg clk = 0;
@@ -142,7 +143,8 @@ axis_ram_switch #(
     .M_TOP(M_TOP),
     .M_CONNECT(M_CONNECT),
     .ARB_TYPE(ARB_TYPE),
-    .LSB_PRIORITY(LSB_PRIORITY)
+    .LSB_PRIORITY(LSB_PRIORITY),
+    .RAM_PIPELINE(RAM_PIPELINE)
 )
 UUT (
     .clk(clk),

fpga/lib/eth/lib/axis/tb/test_axis_ram_switch_4x4_64_64.py

@@ -70,6 +70,7 @@ def bench():
     M_CONNECT = [0b1111]*M_COUNT
     ARB_TYPE = "ROUND_ROBIN"
     LSB_PRIORITY = "HIGH"
+    RAM_PIPELINE = 2
 
     # Inputs
     clk = Signal(bool(0))

fpga/lib/eth/lib/axis/tb/test_axis_ram_switch_4x4_64_64.v

@@ -56,6 +56,7 @@ parameter M_TOP = {3'd3, 3'd2, 3'd1, 3'd0};
 parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}};
 parameter ARB_TYPE = "ROUND_ROBIN";
 parameter LSB_PRIORITY = "HIGH";
+parameter RAM_PIPELINE = 2;
 
 // Inputs
 reg clk = 0;
@@ -142,7 +143,8 @@ axis_ram_switch #(
     .M_TOP(M_TOP),
     .M_CONNECT(M_CONNECT),
     .ARB_TYPE(ARB_TYPE),
-    .LSB_PRIORITY(LSB_PRIORITY)
+    .LSB_PRIORITY(LSB_PRIORITY),
+    .RAM_PIPELINE(RAM_PIPELINE)
 )
 UUT (
     .clk(clk),

fpga/lib/eth/rtl/eth_mac_10g_fifo.v

@@ -40,10 +40,12 @@ module eth_mac_10g_fifo #
     parameter ENABLE_DIC = 1,
     parameter MIN_FRAME_LENGTH = 64,
     parameter TX_FIFO_DEPTH = 4096,
+    parameter TX_FIFO_PIPELINE_OUTPUT = 2,
     parameter TX_FRAME_FIFO = 1,
     parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO,
     parameter TX_DROP_WHEN_FULL = 0,
     parameter RX_FIFO_DEPTH = 4096,
+    parameter RX_FIFO_PIPELINE_OUTPUT = 2,
     parameter RX_FRAME_FIFO = 1,
     parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO,
     parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO,
@@ -586,6 +588,7 @@ axis_async_fifo_adapter #(
     .ID_ENABLE(0),
     .DEST_ENABLE(0),
     .USER_ENABLE(1),
+    .PIPELINE_OUTPUT(TX_FIFO_PIPELINE_OUTPUT),
     .USER_WIDTH(TX_USER_WIDTH),
     .FRAME_FIFO(TX_FRAME_FIFO),
     .USER_BAD_FRAME_VALUE(1'b1),
@@ -636,6 +639,7 @@ axis_async_fifo_adapter #(
     .ID_ENABLE(0),
     .DEST_ENABLE(0),
     .USER_ENABLE(1),
+    .PIPELINE_OUTPUT(RX_FIFO_PIPELINE_OUTPUT),
     .USER_WIDTH(RX_USER_WIDTH),
     .FRAME_FIFO(RX_FRAME_FIFO),
     .USER_BAD_FRAME_VALUE(1'b1),

fpga/lib/eth/rtl/eth_mac_1g_gmii_fifo.v

@@ -48,10 +48,12 @@ module eth_mac_1g_gmii_fifo #
     parameter ENABLE_PADDING = 1,
     parameter MIN_FRAME_LENGTH = 64,
     parameter TX_FIFO_DEPTH = 4096,
+    parameter TX_FIFO_PIPELINE_OUTPUT = 2,
     parameter TX_FRAME_FIFO = 1,
     parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO,
     parameter TX_DROP_WHEN_FULL = 0,
     parameter RX_FIFO_DEPTH = 4096,
+    parameter RX_FIFO_PIPELINE_OUTPUT = 2,
     parameter RX_FRAME_FIFO = 1,
     parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO,
     parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO
@@ -254,6 +256,7 @@ axis_async_fifo_adapter #(
     .DEST_ENABLE(0),
     .USER_ENABLE(1),
     .USER_WIDTH(1),
+    .PIPELINE_OUTPUT(TX_FIFO_PIPELINE_OUTPUT),
     .FRAME_FIFO(TX_FRAME_FIFO),
     .USER_BAD_FRAME_VALUE(1'b1),
     .USER_BAD_FRAME_MASK(1'b1),
@@ -303,6 +306,7 @@ axis_async_fifo_adapter #(
     .DEST_ENABLE(0),
     .USER_ENABLE(1),
     .USER_WIDTH(1),
+    .PIPELINE_OUTPUT(RX_FIFO_PIPELINE_OUTPUT),
     .FRAME_FIFO(RX_FRAME_FIFO),
     .USER_BAD_FRAME_VALUE(1'b1),
     .USER_BAD_FRAME_MASK(1'b1),

fpga/lib/eth/rtl/eth_mac_1g_rgmii_fifo.v

@@ -50,10 +50,12 @@ module eth_mac_1g_rgmii_fifo #
     parameter ENABLE_PADDING = 1,
     parameter MIN_FRAME_LENGTH = 64,
     parameter TX_FIFO_DEPTH = 4096,
+    parameter TX_FIFO_PIPELINE_OUTPUT = 2,
     parameter TX_FRAME_FIFO = 1,
     parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO,
     parameter TX_DROP_WHEN_FULL = 0,
     parameter RX_FIFO_DEPTH = 4096,
+    parameter RX_FIFO_PIPELINE_OUTPUT = 2,
     parameter RX_FRAME_FIFO = 1,
     parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO,
     parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO
@@ -253,6 +255,7 @@ axis_async_fifo_adapter #(
     .DEST_ENABLE(0),
     .USER_ENABLE(1),
     .USER_WIDTH(1),
+    .PIPELINE_OUTPUT(TX_FIFO_PIPELINE_OUTPUT),
     .FRAME_FIFO(TX_FRAME_FIFO),
     .USER_BAD_FRAME_VALUE(1'b1),
     .USER_BAD_FRAME_MASK(1'b1),
@@ -302,6 +305,7 @@ axis_async_fifo_adapter #(
     .DEST_ENABLE(0),
     .USER_ENABLE(1),
     .USER_WIDTH(1),
+    .PIPELINE_OUTPUT(RX_FIFO_PIPELINE_OUTPUT),
     .FRAME_FIFO(RX_FRAME_FIFO),
     .USER_BAD_FRAME_VALUE(1'b1),
     .USER_BAD_FRAME_MASK(1'b1),

fpga/lib/eth/rtl/eth_mac_mii_fifo.v

@@ -44,10 +44,12 @@ module eth_mac_mii_fifo #
     parameter ENABLE_PADDING = 1,
     parameter MIN_FRAME_LENGTH = 64,
     parameter TX_FIFO_DEPTH = 4096,
+    parameter TX_FIFO_PIPELINE_OUTPUT = 2,
     parameter TX_FRAME_FIFO = 1,
     parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO,
     parameter TX_DROP_WHEN_FULL = 0,
     parameter RX_FIFO_DEPTH = 4096,
+    parameter RX_FIFO_PIPELINE_OUTPUT = 2,
     parameter RX_FRAME_FIFO = 1,
     parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO,
     parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO
@@ -231,6 +233,7 @@ axis_async_fifo_adapter #(
     .DEST_ENABLE(0),
     .USER_ENABLE(1),
     .USER_WIDTH(1),
+    .PIPELINE_OUTPUT(TX_FIFO_PIPELINE_OUTPUT),
     .FRAME_FIFO(TX_FRAME_FIFO),
     .USER_BAD_FRAME_VALUE(1'b1),
     .USER_BAD_FRAME_MASK(1'b1),
@@ -280,6 +283,7 @@ axis_async_fifo_adapter #(
     .DEST_ENABLE(0),
     .USER_ENABLE(1),
     .USER_WIDTH(1),
+    .PIPELINE_OUTPUT(RX_FIFO_PIPELINE_OUTPUT),
     .FRAME_FIFO(RX_FRAME_FIFO),
     .USER_BAD_FRAME_VALUE(1'b1),
     .USER_BAD_FRAME_MASK(1'b1),

fpga/lib/eth/rtl/eth_mac_phy_10g_fifo.v

@@ -47,10 +47,12 @@ module eth_mac_phy_10g_fifo #
     parameter SLIP_COUNT_WIDTH = 3,
     parameter COUNT_125US = 125000/6.4,
     parameter TX_FIFO_DEPTH = 4096,
+    parameter TX_FIFO_PIPELINE_OUTPUT = 2,
     parameter TX_FRAME_FIFO = 1,
     parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO,
     parameter TX_DROP_WHEN_FULL = 0,
     parameter RX_FIFO_DEPTH = 4096,
+    parameter RX_FIFO_PIPELINE_OUTPUT = 2,
     parameter RX_FRAME_FIFO = 1,
     parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO,
     parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO,
@@ -616,6 +618,7 @@ axis_async_fifo_adapter #(
     .ID_ENABLE(0),
     .DEST_ENABLE(0),
     .USER_ENABLE(1),
+    .PIPELINE_OUTPUT(TX_FIFO_PIPELINE_OUTPUT),
     .USER_WIDTH(TX_USER_WIDTH),
     .FRAME_FIFO(TX_FRAME_FIFO),
     .USER_BAD_FRAME_VALUE(1'b1),
@@ -666,6 +669,7 @@ axis_async_fifo_adapter #(
     .ID_ENABLE(0),
     .DEST_ENABLE(0),
     .USER_ENABLE(1),
+    .PIPELINE_OUTPUT(RX_FIFO_PIPELINE_OUTPUT),
     .USER_WIDTH(RX_USER_WIDTH),
     .FRAME_FIFO(RX_FRAME_FIFO),
     .USER_BAD_FRAME_VALUE(1'b1),

fpga/lib/eth/scripts/dev-netns-shell.sh

@@ -0,0 +1,68 @@
+#!/bin/bash
+
+ns=""
+
+while getopts h-: option; do
+    case "${option}" in
+        -)
+            case "${OPTARG}" in
+                ns)
+                    val="${!OPTIND}"; OPTIND=$(( $OPTIND + 1 ))
+                    ns=$val
+                    ;;
+                ns=*)
+                    val=${OPTARG#*=}
+                    ns=$val
+                    ;;
+                *)
+                    if [ "$OPTERR" = 1 ] && [ "${optspec:0:1}" != ":" ]; then
+                        echo "Unknown option --${OPTARG}" >&2
+                    fi
+                    ;;
+            esac;;
+        h)
+            echo $(basename $0): usage: $(basename $0) [-h] [--ns=name] [dev] [dev]
+            exit 0
+            ;;
+    esac
+done
+shift $((OPTIND -1))
+
+dev=$1
+
+if [ -z "$ns" ]; then
+    if [ -z "$dev" ]; then
+        echo "Error: must specify either device or network namespace name"
+        exit 1
+    fi
+
+    ns=$dev
+fi
+
+if [ -f "/var/run/netns/$ns" ]; then
+    echo "Network namespace '$ns' already exists"
+else
+    echo "Creating network namespace '$ns'"
+    ip netns add $ns
+    for d in "$@"
+    do
+        echo "Adding interface '$d' to network namespace '$ns'"
+        ip link set dev $d netns $ns
+        ip netns exec $ns ip link set dev $d up
+    done
+fi
+
+if [ -f "/var/run/netns/$ns" ]; then
+    echo "Starting shell in network namespace '$ns'"
+    echo "Note: \$dev='$dev'"
+    export dev
+    ip netns exec $ns bash
+else
+    echo "Error: network namespace not found"
+fi
+
+if [ -f "/var/run/netns/$ns" -a -z "$(ip netns pids $ns)" ]; then
+    echo "Deleting network namespace '$ns'"
+    ip netns del $ns
+fi
+

fpga/lib/eth/scripts/udp_test.py

@@ -0,0 +1,60 @@
+#!/usr/bin/env python
+"""
+UDP echo test
+"""
+
+import argparse
+import socket
+
+def main():
+    parser = argparse.ArgumentParser(description=__doc__.strip())
+    parser.add_argument('host', help="Host")
+    parser.add_argument('port', help="UDP port", nargs='?', type=int, default=1234)
+    parser.add_argument('-n', help="Number of packets", type=int, default=1000)
+
+    args = parser.parse_args()
+    
+    host = args.host
+    port = args.port
+    n = args.n
+    
+    sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)
+    sock.settimeout(0)
+    
+    sent = 0
+    recv = 0
+    
+    data = b'testing'*100
+    
+    print(f"Sending {n} UDP packets to {host} on {port}...")
+    
+    while sent < n:
+        try:
+            sock.sendto(data, (host, port))
+            sent += 1
+        except BlockingIOError:
+            pass
+        
+        try:
+            ret = sock.recvfrom(1024)
+            recv += 1
+        except BlockingIOError:
+            pass
+
+    sock.settimeout(1)
+    
+    while True:
+    
+        try:
+            ret = sock.recvfrom(1024)
+            recv += 1
+        except socket.timeout:
+            break
+    
+    print(f"Sent {sent} packets")
+    print(f"Received {recv} packets ({recv/sent*100}%)")
+    print(f"Missed {sent-recv} packets ({(sent-recv)/sent*100}%)")
+
+
+if __name__ == "__main__":
+    main()

fpga/lib/eth/tb/test_eth_mac_10g_fifo_32.py

@@ -60,10 +60,12 @@ def bench():
     ENABLE_DIC = 1
     MIN_FRAME_LENGTH = 64
     TX_FIFO_DEPTH = 4096
+    TX_FIFO_PIPELINE_OUTPUT = 2
     TX_FRAME_FIFO = 1
     TX_DROP_BAD_FRAME = TX_FRAME_FIFO
     TX_DROP_WHEN_FULL = 0
     RX_FIFO_DEPTH = 4096
+    RX_FIFO_PIPELINE_OUTPUT = 2
     RX_FRAME_FIFO = 1
     RX_DROP_BAD_FRAME = RX_FRAME_FIFO
     RX_DROP_WHEN_FULL = RX_FRAME_FIFO

fpga/lib/eth/tb/test_eth_mac_10g_fifo_32.v

@@ -41,10 +41,12 @@ parameter ENABLE_PADDING = 1;
 parameter ENABLE_DIC = 1;
 parameter MIN_FRAME_LENGTH = 64;
 parameter TX_FIFO_DEPTH = 4096;
+parameter TX_FIFO_PIPELINE_OUTPUT = 2;
 parameter TX_FRAME_FIFO = 1;
 parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO;
 parameter TX_DROP_WHEN_FULL = 0;
 parameter RX_FIFO_DEPTH = 4096;
+parameter RX_FIFO_PIPELINE_OUTPUT = 2;
 parameter RX_FRAME_FIFO = 1;
 parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO;
 parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO;
@@ -146,10 +148,12 @@ eth_mac_10g_fifo #(
     .ENABLE_DIC(ENABLE_DIC),
     .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
     .TX_FIFO_DEPTH(TX_FIFO_DEPTH),
+    .TX_FIFO_PIPELINE_OUTPUT(TX_FIFO_PIPELINE_OUTPUT),
     .TX_FRAME_FIFO(TX_FRAME_FIFO),
     .TX_DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
     .TX_DROP_WHEN_FULL(TX_DROP_WHEN_FULL),
     .RX_FIFO_DEPTH(RX_FIFO_DEPTH),
+    .RX_FIFO_PIPELINE_OUTPUT(RX_FIFO_PIPELINE_OUTPUT),
     .RX_FRAME_FIFO(RX_FRAME_FIFO),
     .RX_DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
     .RX_DROP_WHEN_FULL(RX_DROP_WHEN_FULL)

fpga/lib/eth/tb/test_eth_mac_10g_fifo_64.py

@@ -60,10 +60,12 @@ def bench():
     ENABLE_DIC = 1
     MIN_FRAME_LENGTH = 64
     TX_FIFO_DEPTH = 4096
+    TX_FIFO_PIPELINE_OUTPUT = 2
     TX_FRAME_FIFO = 1
     TX_DROP_BAD_FRAME = TX_FRAME_FIFO
     TX_DROP_WHEN_FULL = 0
     RX_FIFO_DEPTH = 4096
+    RX_FIFO_PIPELINE_OUTPUT = 2
     RX_FRAME_FIFO = 1
     RX_DROP_BAD_FRAME = RX_FRAME_FIFO
     RX_DROP_WHEN_FULL = RX_FRAME_FIFO

fpga/lib/eth/tb/test_eth_mac_10g_fifo_64.v

@@ -41,10 +41,12 @@ parameter ENABLE_PADDING = 1;
 parameter ENABLE_DIC = 1;
 parameter MIN_FRAME_LENGTH = 64;
 parameter TX_FIFO_DEPTH = 4096;
+parameter TX_FIFO_PIPELINE_OUTPUT = 2;
 parameter TX_FRAME_FIFO = 1;
 parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO;
 parameter TX_DROP_WHEN_FULL = 0;
 parameter RX_FIFO_DEPTH = 4096;
+parameter RX_FIFO_PIPELINE_OUTPUT = 2;
 parameter RX_FRAME_FIFO = 1;
 parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO;
 parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO;
@@ -146,10 +148,12 @@ eth_mac_10g_fifo #(
     .ENABLE_DIC(ENABLE_DIC),
     .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
     .TX_FIFO_DEPTH(TX_FIFO_DEPTH),
+    .TX_FIFO_PIPELINE_OUTPUT(TX_FIFO_PIPELINE_OUTPUT),
     .TX_FRAME_FIFO(TX_FRAME_FIFO),
     .TX_DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
     .TX_DROP_WHEN_FULL(TX_DROP_WHEN_FULL),
     .RX_FIFO_DEPTH(RX_FIFO_DEPTH),
+    .RX_FIFO_PIPELINE_OUTPUT(RX_FIFO_PIPELINE_OUTPUT),
     .RX_FRAME_FIFO(RX_FRAME_FIFO),
     .RX_DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
     .RX_DROP_WHEN_FULL(RX_DROP_WHEN_FULL)

fpga/lib/eth/tb/test_eth_mac_10g_fifo_ptp_32.py

@@ -65,10 +65,12 @@ def bench():
     ENABLE_DIC = 1
     MIN_FRAME_LENGTH = 64
     TX_FIFO_DEPTH = 4096
+    TX_FIFO_PIPELINE_OUTPUT = 2
     TX_FRAME_FIFO = 1
     TX_DROP_BAD_FRAME = TX_FRAME_FIFO
     TX_DROP_WHEN_FULL = 0
     RX_FIFO_DEPTH = 4096
+    RX_FIFO_PIPELINE_OUTPUT = 2
     RX_FRAME_FIFO = 1
     RX_DROP_BAD_FRAME = RX_FRAME_FIFO
     RX_DROP_WHEN_FULL = RX_FRAME_FIFO

fpga/lib/eth/tb/test_eth_mac_10g_fifo_ptp_32.v

@@ -41,10 +41,12 @@ parameter ENABLE_PADDING = 1;
 parameter ENABLE_DIC = 1;
 parameter MIN_FRAME_LENGTH = 64;
 parameter TX_FIFO_DEPTH = 4096;
+parameter TX_FIFO_PIPELINE_OUTPUT = 2;
 parameter TX_FRAME_FIFO = 1;
 parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO;
 parameter TX_DROP_WHEN_FULL = 0;
 parameter RX_FIFO_DEPTH = 4096;
+parameter RX_FIFO_PIPELINE_OUTPUT = 2;
 parameter RX_FRAME_FIFO = 1;
 parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO;
 parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO;
@@ -182,10 +184,12 @@ eth_mac_10g_fifo #(
     .ENABLE_DIC(ENABLE_DIC),
     .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
     .TX_FIFO_DEPTH(TX_FIFO_DEPTH),
+    .TX_FIFO_PIPELINE_OUTPUT(TX_FIFO_PIPELINE_OUTPUT),
     .TX_FRAME_FIFO(TX_FRAME_FIFO),
     .TX_DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
     .TX_DROP_WHEN_FULL(TX_DROP_WHEN_FULL),
     .RX_FIFO_DEPTH(RX_FIFO_DEPTH),
+    .RX_FIFO_PIPELINE_OUTPUT(RX_FIFO_PIPELINE_OUTPUT),
     .RX_FRAME_FIFO(RX_FRAME_FIFO),
     .RX_DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
     .RX_DROP_WHEN_FULL(RX_DROP_WHEN_FULL),

fpga/lib/eth/tb/test_eth_mac_10g_fifo_ptp_64.py

@@ -65,10 +65,12 @@ def bench():
     ENABLE_DIC = 1
     MIN_FRAME_LENGTH = 64
     TX_FIFO_DEPTH = 4096
+    TX_FIFO_PIPELINE_OUTPUT = 2
     TX_FRAME_FIFO = 1
     TX_DROP_BAD_FRAME = TX_FRAME_FIFO
     TX_DROP_WHEN_FULL = 0
     RX_FIFO_DEPTH = 4096
+    RX_FIFO_PIPELINE_OUTPUT = 2
     RX_FRAME_FIFO = 1
     RX_DROP_BAD_FRAME = RX_FRAME_FIFO
     RX_DROP_WHEN_FULL = RX_FRAME_FIFO

fpga/lib/eth/tb/test_eth_mac_10g_fifo_ptp_64.v

@@ -41,10 +41,12 @@ parameter ENABLE_PADDING = 1;
 parameter ENABLE_DIC = 1;
 parameter MIN_FRAME_LENGTH = 64;
 parameter TX_FIFO_DEPTH = 4096;
+parameter TX_FIFO_PIPELINE_OUTPUT = 2;
 parameter TX_FRAME_FIFO = 1;
 parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO;
 parameter TX_DROP_WHEN_FULL = 0;
 parameter RX_FIFO_DEPTH = 4096;
+parameter RX_FIFO_PIPELINE_OUTPUT = 2;
 parameter RX_FRAME_FIFO = 1;
 parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO;
 parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO;
@@ -182,10 +184,12 @@ eth_mac_10g_fifo #(
     .ENABLE_DIC(ENABLE_DIC),
     .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
     .TX_FIFO_DEPTH(TX_FIFO_DEPTH),
+    .TX_FIFO_PIPELINE_OUTPUT(TX_FIFO_PIPELINE_OUTPUT),
     .TX_FRAME_FIFO(TX_FRAME_FIFO),
     .TX_DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
     .TX_DROP_WHEN_FULL(TX_DROP_WHEN_FULL),
     .RX_FIFO_DEPTH(RX_FIFO_DEPTH),
+    .RX_FIFO_PIPELINE_OUTPUT(RX_FIFO_PIPELINE_OUTPUT),
     .RX_FRAME_FIFO(RX_FRAME_FIFO),
     .RX_DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
     .RX_DROP_WHEN_FULL(RX_DROP_WHEN_FULL),

fpga/lib/eth/tb/test_eth_mac_1g_fifo.py

@@ -57,10 +57,12 @@ def bench():
     ENABLE_PADDING = 1
     MIN_FRAME_LENGTH = 64
     TX_FIFO_DEPTH = 4096
+    TX_FIFO_PIPELINE_OUTPUT = 2
     TX_FRAME_FIFO = 1
     TX_DROP_BAD_FRAME = TX_FRAME_FIFO
     TX_DROP_WHEN_FULL = 0
     RX_FIFO_DEPTH = 4096
+    RX_FIFO_PIPELINE_OUTPUT = 2
     RX_FRAME_FIFO = 1
     RX_DROP_BAD_FRAME = RX_FRAME_FIFO
     RX_DROP_WHEN_FULL = RX_FRAME_FIFO

fpga/lib/eth/tb/test_eth_mac_1g_fifo.v

@@ -38,10 +38,12 @@ parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8);
 parameter ENABLE_PADDING = 1;
 parameter MIN_FRAME_LENGTH = 64;
 parameter TX_FIFO_DEPTH = 4096;
+parameter TX_FIFO_PIPELINE_OUTPUT = 2;
 parameter TX_FRAME_FIFO = 1;
 parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO;
 parameter TX_DROP_WHEN_FULL = 0;
 parameter RX_FIFO_DEPTH = 4096;
+parameter RX_FIFO_PIPELINE_OUTPUT = 2;
 parameter RX_FRAME_FIFO = 1;
 parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO;
 parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO;
@@ -152,10 +154,12 @@ eth_mac_1g_fifo #(
     .ENABLE_PADDING(ENABLE_PADDING),
     .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
     .TX_FIFO_DEPTH(TX_FIFO_DEPTH),
+    .TX_FIFO_PIPELINE_OUTPUT(TX_FIFO_PIPELINE_OUTPUT),
     .TX_FRAME_FIFO(TX_FRAME_FIFO),
     .TX_DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
     .TX_DROP_WHEN_FULL(TX_DROP_WHEN_FULL),
     .RX_FIFO_DEPTH(RX_FIFO_DEPTH),
+    .RX_FIFO_PIPELINE_OUTPUT(RX_FIFO_PIPELINE_OUTPUT),
     .RX_FRAME_FIFO(RX_FRAME_FIFO),
     .RX_DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
     .RX_DROP_WHEN_FULL(RX_DROP_WHEN_FULL)

fpga/lib/eth/tb/test_eth_mac_1g_gmii_fifo.py

@@ -65,10 +65,12 @@ def bench():
     ENABLE_PADDING = 1
     MIN_FRAME_LENGTH = 64
     TX_FIFO_DEPTH = 4096
+    TX_FIFO_PIPELINE_OUTPUT = 2
     TX_FRAME_FIFO = 1
     TX_DROP_BAD_FRAME = TX_FRAME_FIFO
     TX_DROP_WHEN_FULL = 0
     RX_FIFO_DEPTH = 4096
+    RX_FIFO_PIPELINE_OUTPUT = 2
     RX_FRAME_FIFO = 1
     RX_DROP_BAD_FRAME = RX_FRAME_FIFO
     RX_DROP_WHEN_FULL = RX_FRAME_FIFO

fpga/lib/eth/tb/test_eth_mac_1g_gmii_fifo.v

@@ -41,10 +41,12 @@ parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8);
 parameter ENABLE_PADDING = 1;
 parameter MIN_FRAME_LENGTH = 64;
 parameter TX_FIFO_DEPTH = 4096;
+parameter TX_FIFO_PIPELINE_OUTPUT = 2;
 parameter TX_FRAME_FIFO = 1;
 parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO;
 parameter TX_DROP_WHEN_FULL = 0;
 parameter RX_FIFO_DEPTH = 4096;
+parameter RX_FIFO_PIPELINE_OUTPUT = 2;
 parameter RX_FRAME_FIFO = 1;
 parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO;
 parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO;
@@ -154,10 +156,12 @@ eth_mac_1g_gmii_fifo #(
     .ENABLE_PADDING(ENABLE_PADDING),
     .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
     .TX_FIFO_DEPTH(TX_FIFO_DEPTH),
+    .TX_FIFO_PIPELINE_OUTPUT(TX_FIFO_PIPELINE_OUTPUT),
     .TX_FRAME_FIFO(TX_FRAME_FIFO),
     .TX_DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
     .TX_DROP_WHEN_FULL(TX_DROP_WHEN_FULL),
     .RX_FIFO_DEPTH(RX_FIFO_DEPTH),
+    .RX_FIFO_PIPELINE_OUTPUT(RX_FIFO_PIPELINE_OUTPUT),
     .RX_FRAME_FIFO(RX_FRAME_FIFO),
     .RX_DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
     .RX_DROP_WHEN_FULL(RX_DROP_WHEN_FULL)

fpga/lib/eth/tb/test_eth_mac_1g_rgmii_fifo.py

@@ -67,10 +67,12 @@ def bench():
     ENABLE_PADDING = 1
     MIN_FRAME_LENGTH = 64
     TX_FIFO_DEPTH = 4096
+    TX_FIFO_PIPELINE_OUTPUT = 2
     TX_FRAME_FIFO = 1
     TX_DROP_BAD_FRAME = TX_FRAME_FIFO
     TX_DROP_WHEN_FULL = 0
     RX_FIFO_DEPTH = 4096
+    RX_FIFO_PIPELINE_OUTPUT = 2
     RX_FRAME_FIFO = 1
     RX_DROP_BAD_FRAME = RX_FRAME_FIFO
     RX_DROP_WHEN_FULL = RX_FRAME_FIFO

fpga/lib/eth/tb/test_eth_mac_1g_rgmii_fifo.v

@@ -42,10 +42,12 @@ parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8);
 parameter ENABLE_PADDING = 1;
 parameter MIN_FRAME_LENGTH = 64;
 parameter TX_FIFO_DEPTH = 4096;
+parameter TX_FIFO_PIPELINE_OUTPUT = 2;
 parameter TX_FRAME_FIFO = 1;
 parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO;
 parameter TX_DROP_WHEN_FULL = 0;
 parameter RX_FIFO_DEPTH = 4096;
+parameter RX_FIFO_PIPELINE_OUTPUT = 2;
 parameter RX_FRAME_FIFO = 1;
 parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO;
 parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO;
@@ -152,10 +154,12 @@ eth_mac_1g_rgmii_fifo #(
     .ENABLE_PADDING(ENABLE_PADDING),
     .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
     .TX_FIFO_DEPTH(TX_FIFO_DEPTH),
+    .TX_FIFO_PIPELINE_OUTPUT(TX_FIFO_PIPELINE_OUTPUT),
     .TX_FRAME_FIFO(TX_FRAME_FIFO),
     .TX_DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
     .TX_DROP_WHEN_FULL(TX_DROP_WHEN_FULL),
     .RX_FIFO_DEPTH(RX_FIFO_DEPTH),
+    .RX_FIFO_PIPELINE_OUTPUT(RX_FIFO_PIPELINE_OUTPUT),
     .RX_FRAME_FIFO(RX_FRAME_FIFO),
     .RX_DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
     .RX_DROP_WHEN_FULL(RX_DROP_WHEN_FULL)

fpga/lib/eth/tb/test_eth_mac_mii_fifo.py

@@ -62,10 +62,12 @@ def bench():
     ENABLE_PADDING = 1
     MIN_FRAME_LENGTH = 64
     TX_FIFO_DEPTH = 4096
+    TX_FIFO_PIPELINE_OUTPUT = 2
     TX_FRAME_FIFO = 1
     TX_DROP_BAD_FRAME = TX_FRAME_FIFO
     TX_DROP_WHEN_FULL = 0
     RX_FIFO_DEPTH = 4096
+    RX_FIFO_PIPELINE_OUTPUT = 2
     RX_FRAME_FIFO = 1
     RX_DROP_BAD_FRAME = RX_FRAME_FIFO
     RX_DROP_WHEN_FULL = RX_FRAME_FIFO

fpga/lib/eth/tb/test_eth_mac_mii_fifo.v

@@ -40,10 +40,12 @@ parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8);
 parameter ENABLE_PADDING = 1;
 parameter MIN_FRAME_LENGTH = 64;
 parameter TX_FIFO_DEPTH = 4096;
+parameter TX_FIFO_PIPELINE_OUTPUT = 2;
 parameter TX_FRAME_FIFO = 1;
 parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO;
 parameter TX_DROP_WHEN_FULL = 0;
 parameter RX_FIFO_DEPTH = 4096;
+parameter RX_FIFO_PIPELINE_OUTPUT = 2;
 parameter RX_FRAME_FIFO = 1;
 parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO;
 parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO;
@@ -144,10 +146,12 @@ eth_mac_mii_fifo #(
     .ENABLE_PADDING(ENABLE_PADDING),
     .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
     .TX_FIFO_DEPTH(TX_FIFO_DEPTH),
+    .TX_FIFO_PIPELINE_OUTPUT(TX_FIFO_PIPELINE_OUTPUT),
     .TX_FRAME_FIFO(TX_FRAME_FIFO),
     .TX_DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
     .TX_DROP_WHEN_FULL(TX_DROP_WHEN_FULL),
     .RX_FIFO_DEPTH(RX_FIFO_DEPTH),
+    .RX_FIFO_PIPELINE_OUTPUT(RX_FIFO_PIPELINE_OUTPUT),
     .RX_FRAME_FIFO(RX_FRAME_FIFO),
     .RX_DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
     .RX_DROP_WHEN_FULL(RX_DROP_WHEN_FULL)

fpga/lib/eth/tb/test_eth_mac_phy_10g_fifo.py

@@ -74,10 +74,12 @@ def bench():
     SLIP_COUNT_WIDTH = 3
     COUNT_125US = 125000/6.4
     TX_FIFO_DEPTH = 4096
+    TX_FIFO_PIPELINE_OUTPUT = 2
     TX_FRAME_FIFO = 1
     TX_DROP_BAD_FRAME = TX_FRAME_FIFO
     TX_DROP_WHEN_FULL = 0
     RX_FIFO_DEPTH = 4096
+    RX_FIFO_PIPELINE_OUTPUT = 2
     RX_FRAME_FIFO = 1
     RX_DROP_BAD_FRAME = RX_FRAME_FIFO
     RX_DROP_WHEN_FULL = RX_FRAME_FIFO

fpga/lib/eth/tb/test_eth_mac_phy_10g_fifo.v

@@ -48,10 +48,12 @@ parameter RX_SERDES_PIPELINE = 2;
 parameter SLIP_COUNT_WIDTH = 3;
 parameter COUNT_125US = 125000/6.4;
 parameter TX_FIFO_DEPTH = 4096;
+parameter TX_FIFO_PIPELINE_OUTPUT = 2;
 parameter TX_FRAME_FIFO = 1;
 parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO;
 parameter TX_DROP_WHEN_FULL = 0;
 parameter RX_FIFO_DEPTH = 4096;
+parameter RX_FIFO_PIPELINE_OUTPUT = 2;
 parameter RX_FRAME_FIFO = 1;
 parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO;
 parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO;
@@ -172,10 +174,12 @@ eth_mac_phy_10g_fifo #(
     .SLIP_COUNT_WIDTH(SLIP_COUNT_WIDTH),
     .COUNT_125US(COUNT_125US),
     .TX_FIFO_DEPTH(TX_FIFO_DEPTH),
+    .TX_FIFO_PIPELINE_OUTPUT(TX_FIFO_PIPELINE_OUTPUT),
     .TX_FRAME_FIFO(TX_FRAME_FIFO),
     .TX_DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
     .TX_DROP_WHEN_FULL(TX_DROP_WHEN_FULL),
     .RX_FIFO_DEPTH(RX_FIFO_DEPTH),
+    .RX_FIFO_PIPELINE_OUTPUT(RX_FIFO_PIPELINE_OUTPUT),
     .RX_FRAME_FIFO(RX_FRAME_FIFO),
     .RX_DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
     .RX_DROP_WHEN_FULL(RX_DROP_WHEN_FULL)

fpga/lib/eth/tb/test_eth_mac_phy_10g_fifo_ptp.py

@@ -79,10 +79,12 @@ def bench():
     SLIP_COUNT_WIDTH = 3
     COUNT_125US = 125000/6.4
     TX_FIFO_DEPTH = 4096
+    TX_FIFO_PIPELINE_OUTPUT = 2
     TX_FRAME_FIFO = 1
     TX_DROP_BAD_FRAME = TX_FRAME_FIFO
     TX_DROP_WHEN_FULL = 0
     RX_FIFO_DEPTH = 4096
+    RX_FIFO_PIPELINE_OUTPUT = 2
     RX_FRAME_FIFO = 1
     RX_DROP_BAD_FRAME = RX_FRAME_FIFO
     RX_DROP_WHEN_FULL = RX_FRAME_FIFO

fpga/lib/eth/tb/test_eth_mac_phy_10g_fifo_ptp.v

@@ -48,10 +48,12 @@ parameter RX_SERDES_PIPELINE = 2;
 parameter SLIP_COUNT_WIDTH = 3;
 parameter COUNT_125US = 125000/6.4;
 parameter TX_FIFO_DEPTH = 4096;
+parameter TX_FIFO_PIPELINE_OUTPUT = 2;
 parameter TX_FRAME_FIFO = 1;
 parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO;
 parameter TX_DROP_WHEN_FULL = 0;
 parameter RX_FIFO_DEPTH = 4096;
+parameter RX_FIFO_PIPELINE_OUTPUT = 2;
 parameter RX_FRAME_FIFO = 1;
 parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO;
 parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO;
@@ -208,10 +210,12 @@ eth_mac_phy_10g_fifo #(
     .SLIP_COUNT_WIDTH(SLIP_COUNT_WIDTH),
     .COUNT_125US(COUNT_125US),
     .TX_FIFO_DEPTH(TX_FIFO_DEPTH),
+    .TX_FIFO_PIPELINE_OUTPUT(TX_FIFO_PIPELINE_OUTPUT),
     .TX_FRAME_FIFO(TX_FRAME_FIFO),
     .TX_DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
     .TX_DROP_WHEN_FULL(TX_DROP_WHEN_FULL),
     .RX_FIFO_DEPTH(RX_FIFO_DEPTH),
+    .RX_FIFO_PIPELINE_OUTPUT(RX_FIFO_PIPELINE_OUTPUT),
     .RX_FRAME_FIFO(RX_FRAME_FIFO),
     .RX_DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
     .RX_DROP_WHEN_FULL(RX_DROP_WHEN_FULL),