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Rewrite op tag FIFO read in DMA engines

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This commit is contained in:
Alex Forencich 2021-10-31 21:57:26 -07:00
parent 482b305913
commit f612d88288
3 changed files with 57 additions and 22 deletions
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27
rtl/dma_if_pcie_rd.v
View File

@ -324,6 +324,7 @@ reg [LEN_WIDTH-1:0] req_op_count_reg = {LEN_WIDTH{1'b0}}, req_op_count_next;
reg [12:0] req_tlp_count_reg = 13'd0, req_tlp_count_next;
reg req_zero_len_reg = 1'b0, req_zero_len_next;
reg [OP_TAG_WIDTH-1:0] req_op_tag_reg = {OP_TAG_WIDTH{1'b0}}, req_op_tag_next;
reg req_op_tag_valid_reg = 1'b0, req_op_tag_valid_next;
reg [PCIE_TAG_WIDTH-1:0] req_pcie_tag_reg = {PCIE_TAG_WIDTH{1'b0}}, req_pcie_tag_next;
reg req_pcie_tag_valid_reg = 1'b0, req_pcie_tag_valid_next;
@ -588,12 +589,13 @@ always @* begin
req_tlp_count_next = req_tlp_count_reg;
req_zero_len_next = req_zero_len_reg;
req_op_tag_next = req_op_tag_reg;
req_op_tag_valid_next = req_op_tag_valid_reg;
req_pcie_tag_next = req_pcie_tag_reg;
req_pcie_tag_valid_next = req_pcie_tag_valid_reg;
inc_active_tx = 1'b0;
op_table_start_ptr = op_tag_fifo_mem[op_tag_fifo_rd_ptr_reg[OP_TAG_WIDTH-1:0]];
op_table_start_ptr = req_op_tag_reg;
op_table_start_tag = s_axis_read_desc_tag;
op_table_start_en = 1'b0;
@ -601,8 +603,6 @@ always @* begin
op_table_read_start_commit = 1'b0;
op_table_read_start_en = 1'b0;
op_tag_fifo_rd_ptr_next = op_tag_fifo_rd_ptr_reg;
// TLP size computation
if (req_op_count_reg + req_pcie_addr_reg[1:0] <= {max_read_request_size_dw_reg, 2'b00}) begin
// packet smaller than max read request size
@ -696,7 +696,7 @@ always @* begin
// TLP segmentation and request generation
case (req_state_reg)
REQ_STATE_IDLE: begin
s_axis_read_desc_ready_next = init_done_reg && enable && (op_tag_fifo_rd_ptr_reg != op_tag_fifo_wr_ptr_reg);
s_axis_read_desc_ready_next = init_done_reg && enable && req_op_tag_valid_reg;
if (s_axis_read_desc_ready && s_axis_read_desc_valid) begin
s_axis_read_desc_ready_next = 1'b0;
@ -711,12 +711,10 @@ always @* begin
req_op_count_next = s_axis_read_desc_len;
req_zero_len_next = 1'b0;
end
req_op_tag_next = op_tag_fifo_mem[op_tag_fifo_rd_ptr_reg[OP_TAG_WIDTH-1:0]];
op_table_start_ptr = op_tag_fifo_mem[op_tag_fifo_rd_ptr_reg[OP_TAG_WIDTH-1:0]];
op_table_start_ptr = req_op_tag_reg;
op_table_start_tag = s_axis_read_desc_tag;
op_table_start_en = 1'b1;
op_tag_fifo_rd_ptr_next = op_tag_fifo_rd_ptr_reg+1;
stat_rd_op_start_tag_next = op_tag_fifo_mem[op_tag_fifo_rd_ptr_reg[OP_TAG_WIDTH-1:0]];
stat_rd_op_start_tag_next = req_op_tag_reg;
stat_rd_op_start_len_next = s_axis_read_desc_len;
stat_rd_op_start_valid_next = 1'b1;
req_state_next = REQ_STATE_START;
@ -758,6 +756,7 @@ always @* begin
if (!req_last_tlp) begin
req_state_next = REQ_STATE_START;
end else begin
req_op_tag_valid_next = 1'b0;
s_axis_read_desc_ready_next = init_done_reg && enable && (op_tag_fifo_rd_ptr_reg != op_tag_fifo_wr_ptr_reg);
req_state_next = REQ_STATE_IDLE;
end
@ -767,6 +766,16 @@ always @* begin
end
endcase
op_tag_fifo_rd_ptr_next = op_tag_fifo_rd_ptr_reg;
if (!req_op_tag_valid_next) begin
if (op_tag_fifo_rd_ptr_reg != op_tag_fifo_wr_ptr_reg) begin
req_op_tag_next = op_tag_fifo_mem[op_tag_fifo_rd_ptr_reg[OP_TAG_WIDTH-1:0]];
req_op_tag_valid_next = 1'b1;
op_tag_fifo_rd_ptr_next = op_tag_fifo_rd_ptr_reg + 1;
end
end
pcie_tag_fifo_1_rd_ptr_next = pcie_tag_fifo_1_rd_ptr_reg;
pcie_tag_fifo_2_rd_ptr_next = pcie_tag_fifo_2_rd_ptr_reg;
@ -1299,6 +1308,7 @@ always @(posedge clk) begin
req_tlp_count_reg <= req_tlp_count_next;
req_zero_len_reg <= req_zero_len_next;
req_op_tag_reg <= req_op_tag_next;
req_op_tag_valid_reg <= req_op_tag_valid_next;
req_pcie_tag_reg <= req_pcie_tag_next;
req_pcie_tag_valid_reg <= req_pcie_tag_valid_next;
@ -1474,6 +1484,7 @@ always @(posedge clk) begin
init_pcie_tag_reg <= 1'b1;
init_op_tag_reg <= 1'b1;
req_op_tag_valid_reg <= 1'b0;
req_pcie_tag_valid_reg <= 1'b0;
finish_tag_reg <= 1'b0;

26
rtl/dma_if_pcie_us_rd.v
View File

@ -352,6 +352,7 @@ reg [LEN_WIDTH-1:0] req_op_count_reg = {LEN_WIDTH{1'b0}}, req_op_count_next;
reg [12:0] req_tlp_count_reg = 13'd0, req_tlp_count_next;
reg req_zero_len_reg = 1'b0, req_zero_len_next;
reg [OP_TAG_WIDTH-1:0] req_op_tag_reg = {OP_TAG_WIDTH{1'b0}}, req_op_tag_next;
reg req_op_tag_valid_reg = 1'b0, req_op_tag_valid_next;
reg [PCIE_TAG_WIDTH-1:0] req_pcie_tag_reg = {PCIE_TAG_WIDTH{1'b0}}, req_pcie_tag_next;
reg req_pcie_tag_valid_reg = 1'b0, req_pcie_tag_valid_next;
@ -549,12 +550,13 @@ always @* begin
req_tlp_count_next = req_tlp_count_reg;
req_zero_len_next = req_zero_len_reg;
req_op_tag_next = req_op_tag_reg;
req_op_tag_valid_next = req_op_tag_valid_reg;
req_pcie_tag_next = req_pcie_tag_reg;
req_pcie_tag_valid_next = req_pcie_tag_valid_reg;
inc_active_tx = 1'b0;
op_table_start_ptr = op_tag_fifo_mem[op_tag_fifo_rd_ptr_reg[OP_TAG_WIDTH-1:0]];
op_table_start_ptr = req_op_tag_reg;
op_table_start_tag = s_axis_read_desc_tag;
op_table_start_en = 1'b0;
@ -562,8 +564,6 @@ always @* begin
op_table_read_start_commit = 1'b0;
op_table_read_start_en = 1'b0;
op_tag_fifo_rd_ptr_next = op_tag_fifo_rd_ptr_reg;
// TLP size computation
if (req_op_count_reg + req_pcie_addr_reg[1:0] <= {max_read_request_size_dw_reg, 2'b00}) begin
// packet smaller than max read request size
@ -688,7 +688,7 @@ always @* begin
// TLP segmentation and request generation
case (req_state_reg)
REQ_STATE_IDLE: begin
s_axis_read_desc_ready_next = init_done_reg && enable && (op_tag_fifo_rd_ptr_reg != op_tag_fifo_wr_ptr_reg);
s_axis_read_desc_ready_next = init_done_reg && enable && req_op_tag_valid_reg;
if (s_axis_read_desc_ready && s_axis_read_desc_valid) begin
s_axis_read_desc_ready_next = 1'b0;
@ -703,11 +703,9 @@ always @* begin
req_op_count_next = s_axis_read_desc_len;
req_zero_len_next = 1'b0;
end
req_op_tag_next = op_tag_fifo_mem[op_tag_fifo_rd_ptr_reg[OP_TAG_WIDTH-1:0]];
op_table_start_ptr = op_tag_fifo_mem[op_tag_fifo_rd_ptr_reg[OP_TAG_WIDTH-1:0]];
op_table_start_ptr = req_op_tag_reg;
op_table_start_tag = s_axis_read_desc_tag;
op_table_start_en = 1'b1;
op_tag_fifo_rd_ptr_next = op_tag_fifo_rd_ptr_reg+1;
req_state_next = REQ_STATE_START;
end else begin
req_state_next = REQ_STATE_IDLE;
@ -740,6 +738,7 @@ always @* begin
if (!req_last_tlp) begin
req_state_next = REQ_STATE_START;
end else begin
req_op_tag_valid_next = 1'b0;
s_axis_read_desc_ready_next = init_done_reg && enable && (op_tag_fifo_rd_ptr_reg != op_tag_fifo_wr_ptr_reg);
req_state_next = REQ_STATE_IDLE;
end
@ -779,6 +778,7 @@ always @* begin
if (!req_last_tlp) begin
req_state_next = REQ_STATE_START;
end else begin
req_op_tag_valid_next = 1'b0;
s_axis_read_desc_ready_next = init_done_reg && enable && (op_tag_fifo_rd_ptr_reg != op_tag_fifo_wr_ptr_reg);
req_state_next = REQ_STATE_IDLE;
end
@ -789,6 +789,16 @@ always @* begin
end
endcase
op_tag_fifo_rd_ptr_next = op_tag_fifo_rd_ptr_reg;
if (!req_op_tag_valid_next) begin
if (op_tag_fifo_rd_ptr_reg != op_tag_fifo_wr_ptr_reg) begin
req_op_tag_next = op_tag_fifo_mem[op_tag_fifo_rd_ptr_reg[OP_TAG_WIDTH-1:0]];
req_op_tag_valid_next = 1'b1;
op_tag_fifo_rd_ptr_next = op_tag_fifo_rd_ptr_reg + 1;
end
end
pcie_tag_fifo_1_rd_ptr_next = pcie_tag_fifo_1_rd_ptr_reg;
pcie_tag_fifo_2_rd_ptr_next = pcie_tag_fifo_2_rd_ptr_reg;
@ -1457,6 +1467,7 @@ always @(posedge clk) begin
req_tlp_count_reg <= req_tlp_count_next;
req_zero_len_reg <= req_zero_len_next;
req_op_tag_reg <= req_op_tag_next;
req_op_tag_valid_reg <= req_op_tag_valid_next;
req_pcie_tag_reg <= req_pcie_tag_next;
req_pcie_tag_valid_reg <= req_pcie_tag_valid_next;
@ -1622,6 +1633,7 @@ always @(posedge clk) begin
init_pcie_tag_reg <= 1'b1;
init_op_tag_reg <= 1'b1;
req_op_tag_valid_reg <= 1'b0;
req_pcie_tag_valid_reg <= 1'b0;
finish_tag_reg <= 1'b0;

26
rtl/pcie_us_axi_dma_rd.v
View File

@ -359,6 +359,7 @@ reg [LEN_WIDTH-1:0] req_op_count_reg = {LEN_WIDTH{1'b0}}, req_op_count_next;
reg [12:0] req_tlp_count_reg = 13'd0, req_tlp_count_next;
reg req_zero_len_reg = 1'b0, req_zero_len_next;
reg [OP_TAG_WIDTH-1:0] req_op_tag_reg = {OP_TAG_WIDTH{1'b0}}, req_op_tag_next;
reg req_op_tag_valid_reg = 1'b0, req_op_tag_valid_next;
reg [PCIE_TAG_WIDTH-1:0] req_pcie_tag_reg = {PCIE_TAG_WIDTH{1'b0}}, req_pcie_tag_next;
reg req_pcie_tag_valid_reg = 1'b0, req_pcie_tag_valid_next;
@ -567,12 +568,13 @@ always @* begin
req_tlp_count_next = req_tlp_count_reg;
req_zero_len_next = req_zero_len_reg;
req_op_tag_next = req_op_tag_reg;
req_op_tag_valid_next = req_op_tag_valid_reg;
req_pcie_tag_next = req_pcie_tag_reg;
req_pcie_tag_valid_next = req_pcie_tag_valid_reg;
inc_active_tx = 1'b0;
op_table_start_ptr = op_tag_fifo_mem[op_tag_fifo_rd_ptr_reg[OP_TAG_WIDTH-1:0]];
op_table_start_ptr = req_op_tag_reg;
op_table_start_tag = s_axis_read_desc_tag;
op_table_start_en = 1'b0;
@ -580,8 +582,6 @@ always @* begin
op_table_read_start_commit = 1'b0;
op_table_read_start_en = 1'b0;
op_tag_fifo_rd_ptr_next = op_tag_fifo_rd_ptr_reg;
// TLP size computation
if (req_op_count_reg + req_pcie_addr_reg[1:0] <= {max_read_request_size_dw_reg, 2'b00}) begin
// packet smaller than max read request size
@ -705,7 +705,7 @@ always @* begin
// TLP segmentation and request generation
case (req_state_reg)
REQ_STATE_IDLE: begin
s_axis_read_desc_ready_next = init_done_reg && enable && (op_tag_fifo_rd_ptr_reg != op_tag_fifo_wr_ptr_reg);
s_axis_read_desc_ready_next = init_done_reg && enable && req_op_tag_valid_reg;
if (s_axis_read_desc_ready && s_axis_read_desc_valid) begin
s_axis_read_desc_ready_next = 1'b0;
@ -719,11 +719,9 @@ always @* begin
req_op_count_next = s_axis_read_desc_len;
req_zero_len_next = 1'b0;
end
req_op_tag_next = op_tag_fifo_mem[op_tag_fifo_rd_ptr_reg[OP_TAG_WIDTH-1:0]];
op_table_start_ptr = op_tag_fifo_mem[op_tag_fifo_rd_ptr_reg[OP_TAG_WIDTH-1:0]];
op_table_start_ptr = req_op_tag_reg;
op_table_start_tag = s_axis_read_desc_tag;
op_table_start_en = 1'b1;
op_tag_fifo_rd_ptr_next = op_tag_fifo_rd_ptr_reg+1;
req_state_next = REQ_STATE_START;
end else begin
req_state_next = REQ_STATE_IDLE;
@ -756,6 +754,7 @@ always @* begin
if (!req_last_tlp) begin
req_state_next = REQ_STATE_START;
end else begin
req_op_tag_valid_next = 1'b0;
s_axis_read_desc_ready_next = init_done_reg && enable && (op_tag_fifo_rd_ptr_reg != op_tag_fifo_wr_ptr_reg);
req_state_next = REQ_STATE_IDLE;
end
@ -794,6 +793,7 @@ always @* begin
if (!req_last_tlp) begin
req_state_next = REQ_STATE_START;
end else begin
req_op_tag_valid_next = 1'b0;
s_axis_read_desc_ready_next = init_done_reg && enable && (op_tag_fifo_rd_ptr_reg != op_tag_fifo_wr_ptr_reg);
req_state_next = REQ_STATE_IDLE;
end
@ -804,6 +804,16 @@ always @* begin
end
endcase
op_tag_fifo_rd_ptr_next = op_tag_fifo_rd_ptr_reg;
if (!req_op_tag_valid_next) begin
if (op_tag_fifo_rd_ptr_reg != op_tag_fifo_wr_ptr_reg) begin
req_op_tag_next = op_tag_fifo_mem[op_tag_fifo_rd_ptr_reg[OP_TAG_WIDTH-1:0]];
req_op_tag_valid_next = 1'b1;
op_tag_fifo_rd_ptr_next = op_tag_fifo_rd_ptr_reg + 1;
end
end
pcie_tag_fifo_1_rd_ptr_next = pcie_tag_fifo_1_rd_ptr_reg;
pcie_tag_fifo_2_rd_ptr_next = pcie_tag_fifo_2_rd_ptr_reg;
@ -1474,6 +1484,7 @@ always @(posedge clk) begin
req_tlp_count_reg <= req_tlp_count_next;
req_zero_len_reg <= req_zero_len_next;
req_op_tag_reg <= req_op_tag_next;
req_op_tag_valid_reg <= req_op_tag_valid_next;
req_pcie_tag_reg <= req_pcie_tag_next;
req_pcie_tag_valid_reg <= req_pcie_tag_valid_next;
@ -1644,6 +1655,7 @@ always @(posedge clk) begin
init_pcie_tag_reg <= 1'b1;
init_op_tag_reg <= 1'b1;
req_op_tag_valid_reg <= 1'b0;
req_pcie_tag_valid_reg <= 1'b0;
finish_tag_reg <= 1'b0;