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fpga/mqnic: Update FIFO parameter naming

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2022-11-01 23:57:50 -07:00
parent 0cb106e2aa
commit f6262c3606
5 changed files with 10 additions and 10 deletions
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4
fpga/common/rtl/mqnic_interface.v
View File

@ -2908,7 +2908,7 @@ tx_fifo #(
.M_DEST_WIDTH(AXIS_IF_TX_DEST_WIDTH),
.USER_ENABLE(1),
.USER_WIDTH(AXIS_IF_TX_USER_WIDTH),
.PIPELINE_OUTPUT(AXIS_TX_FIFO_PIPELINE)
.RAM_PIPELINE(AXIS_TX_FIFO_PIPELINE)
)
tx_fifo_inst (
.clk(clk),
@ -2979,7 +2979,7 @@ rx_fifo #(
.DEST_WIDTH(AXIS_IF_RX_DEST_WIDTH),
.USER_ENABLE(1),
.USER_WIDTH(AXIS_IF_RX_USER_WIDTH),
.PIPELINE_OUTPUT(AXIS_RX_FIFO_PIPELINE)
.RAM_PIPELINE(AXIS_RX_FIFO_PIPELINE)
)
rx_fifo_inst (
.clk(clk),

2
fpga/common/rtl/mqnic_interface_rx.v
View File

@ -243,7 +243,7 @@ axis_fifo #(
.ID_WIDTH(DESC_REQ_TAG_WIDTH),
.DEST_ENABLE(0),
.USER_ENABLE(0),
.PIPELINE_OUTPUT(3),
.RAM_PIPELINE(2),
.FRAME_FIFO(0)
)
rx_desc_fifo (

2
fpga/common/rtl/mqnic_interface_tx.v
View File

@ -237,7 +237,7 @@ axis_fifo #(
.ID_WIDTH(DESC_REQ_TAG_WIDTH),
.DEST_ENABLE(0),
.USER_ENABLE(0),
.PIPELINE_OUTPUT(3),
.RAM_PIPELINE(2),
.FRAME_FIFO(0)
)
tx_desc_fifo (

6
fpga/common/rtl/rx_fifo.v
View File

@ -74,8 +74,8 @@ module rx_fifo #
parameter USER_ENABLE = 1,
// tuser signal width
parameter USER_WIDTH = 1,
// number of output pipeline registers
parameter PIPELINE_OUTPUT = 2
// number of RAM pipeline registers
parameter RAM_PIPELINE = 1
)
(
input wire clk,
@ -142,7 +142,7 @@ for (n = 0; n < PORTS; n = n + 1) begin : fifo
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.PIPELINE_OUTPUT(PIPELINE_OUTPUT),
.RAM_PIPELINE(RAM_PIPELINE),
.FRAME_FIFO(1),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),

6
fpga/common/rtl/tx_fifo.v
View File

@ -73,8 +73,8 @@ module tx_fifo #
parameter USER_ENABLE = 1,
// tuser signal width
parameter USER_WIDTH = 1,
// number of output pipeline registers
parameter PIPELINE_OUTPUT = 2
// number of RAM pipeline registers
parameter RAM_PIPELINE = 1
)
(
input wire clk,
@ -200,7 +200,7 @@ for (n = 0; n < PORTS; n = n + 1) begin : fifo
.DEST_WIDTH(M_DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.PIPELINE_OUTPUT(PIPELINE_OUTPUT),
.RAM_PIPELINE(RAM_PIPELINE),
.FRAME_FIFO(1),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),