diff --git a/fpga/common/rtl/mqnic_interface.v b/fpga/common/rtl/mqnic_interface.v
index a2b979121..3550e8a1c 100644
--- a/fpga/common/rtl/mqnic_interface.v
+++ b/fpga/common/rtl/mqnic_interface.v
@@ -2908,7 +2908,7 @@ tx_fifo #(
     .M_DEST_WIDTH(AXIS_IF_TX_DEST_WIDTH),
     .USER_ENABLE(1),
     .USER_WIDTH(AXIS_IF_TX_USER_WIDTH),
-    .PIPELINE_OUTPUT(AXIS_TX_FIFO_PIPELINE)
+    .RAM_PIPELINE(AXIS_TX_FIFO_PIPELINE)
 )
 tx_fifo_inst (
     .clk(clk),
@@ -2979,7 +2979,7 @@ rx_fifo #(
     .DEST_WIDTH(AXIS_IF_RX_DEST_WIDTH),
     .USER_ENABLE(1),
     .USER_WIDTH(AXIS_IF_RX_USER_WIDTH),
-    .PIPELINE_OUTPUT(AXIS_RX_FIFO_PIPELINE)
+    .RAM_PIPELINE(AXIS_RX_FIFO_PIPELINE)
 )
 rx_fifo_inst (
     .clk(clk),
diff --git a/fpga/common/rtl/mqnic_interface_rx.v b/fpga/common/rtl/mqnic_interface_rx.v
index b57cbef51..8b6478c76 100644
--- a/fpga/common/rtl/mqnic_interface_rx.v
+++ b/fpga/common/rtl/mqnic_interface_rx.v
@@ -243,7 +243,7 @@ axis_fifo #(
     .ID_WIDTH(DESC_REQ_TAG_WIDTH),
     .DEST_ENABLE(0),
     .USER_ENABLE(0),
-    .PIPELINE_OUTPUT(3),
+    .RAM_PIPELINE(2),
     .FRAME_FIFO(0)
 )
 rx_desc_fifo (
diff --git a/fpga/common/rtl/mqnic_interface_tx.v b/fpga/common/rtl/mqnic_interface_tx.v
index 7b10b35d2..b955a173c 100644
--- a/fpga/common/rtl/mqnic_interface_tx.v
+++ b/fpga/common/rtl/mqnic_interface_tx.v
@@ -237,7 +237,7 @@ axis_fifo #(
     .ID_WIDTH(DESC_REQ_TAG_WIDTH),
     .DEST_ENABLE(0),
     .USER_ENABLE(0),
-    .PIPELINE_OUTPUT(3),
+    .RAM_PIPELINE(2),
     .FRAME_FIFO(0)
 )
 tx_desc_fifo (
diff --git a/fpga/common/rtl/rx_fifo.v b/fpga/common/rtl/rx_fifo.v
index 8643513bc..8a8dca6c5 100644
--- a/fpga/common/rtl/rx_fifo.v
+++ b/fpga/common/rtl/rx_fifo.v
@@ -74,8 +74,8 @@ module rx_fifo #
     parameter USER_ENABLE = 1,
     // tuser signal width
     parameter USER_WIDTH = 1,
-    // number of output pipeline registers
-    parameter PIPELINE_OUTPUT = 2
+    // number of RAM pipeline registers
+    parameter RAM_PIPELINE = 1
 )
 (
     input  wire                           clk,
@@ -142,7 +142,7 @@ for (n = 0; n < PORTS; n = n + 1) begin : fifo
         .DEST_WIDTH(DEST_WIDTH),
         .USER_ENABLE(USER_ENABLE),
         .USER_WIDTH(USER_WIDTH),
-        .PIPELINE_OUTPUT(PIPELINE_OUTPUT),
+        .RAM_PIPELINE(RAM_PIPELINE),
         .FRAME_FIFO(1),
         .USER_BAD_FRAME_VALUE(1'b1),
         .USER_BAD_FRAME_MASK(1'b1),
diff --git a/fpga/common/rtl/tx_fifo.v b/fpga/common/rtl/tx_fifo.v
index 3e0cdfd52..9d6612ffc 100644
--- a/fpga/common/rtl/tx_fifo.v
+++ b/fpga/common/rtl/tx_fifo.v
@@ -73,8 +73,8 @@ module tx_fifo #
     parameter USER_ENABLE = 1,
     // tuser signal width
     parameter USER_WIDTH = 1,
-    // number of output pipeline registers
-    parameter PIPELINE_OUTPUT = 2
+    // number of RAM pipeline registers
+    parameter RAM_PIPELINE = 1
 )
 (
     input  wire                           clk,
@@ -200,7 +200,7 @@ for (n = 0; n < PORTS; n = n + 1) begin : fifo
         .DEST_WIDTH(M_DEST_WIDTH),
         .USER_ENABLE(USER_ENABLE),
         .USER_WIDTH(USER_WIDTH),
-        .PIPELINE_OUTPUT(PIPELINE_OUTPUT),
+        .RAM_PIPELINE(RAM_PIPELINE),
         .FRAME_FIFO(1),
         .USER_BAD_FRAME_VALUE(1'b1),
         .USER_BAD_FRAME_MASK(1'b1),