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merged changes in axi

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This commit is contained in:
Alex Forencich 2021-12-10 18:50:04 -08:00
commit f8a1339581
21 changed files with 112 additions and 112 deletions
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8
fpga/lib/axi/rtl/axil_register_wr.v
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@ -190,7 +190,7 @@ assign m_axil_awprot = m_axil_awprot_reg;
assign m_axil_awvalid = m_axil_awvalid_reg;
// enable ready input next cycle if output buffer will be empty
wire s_axil_awready_eawly = !m_axil_awvalid_next;
wire s_axil_awready_early = !m_axil_awvalid_next;
always @* begin
// transfer sink ready state to source
@ -211,7 +211,7 @@ always @(posedge clk) begin
s_axil_awready_reg <= 1'b0;
m_axil_awvalid_reg <= 1'b0;
end else begin
s_axil_awready_reg <= s_axil_awready_eawly;
s_axil_awready_reg <= s_axil_awready_early;
m_axil_awvalid_reg <= m_axil_awvalid_next;
end
@ -336,7 +336,7 @@ assign m_axil_wstrb = m_axil_wstrb_reg;
assign m_axil_wvalid = m_axil_wvalid_reg;
// enable ready input next cycle if output buffer will be empty
wire s_axil_wready_ewly = !m_axil_wvalid_next;
wire s_axil_wready_early = !m_axil_wvalid_next;
always @* begin
// transfer sink ready state to source
@ -357,7 +357,7 @@ always @(posedge clk) begin
s_axil_wready_reg <= 1'b0;
m_axil_wvalid_reg <= 1'b0;
end else begin
s_axil_wready_reg <= s_axil_wready_ewly;
s_axil_wready_reg <= s_axil_wready_early;
m_axil_wvalid_reg <= m_axil_wvalid_next;
end

8
fpga/lib/axi/tb/axi_adapter/test_axi_adapter.py
View File

@ -45,7 +45,7 @@ class TB(object):
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.fork(Clock(dut.clk, 10, units="ns").start())
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
self.axi_master = AxiMaster(AxiBus.from_prefix(dut, "s_axi"), dut.clk, dut.rst)
self.axi_ram = AxiRam(AxiBus.from_prefix(dut, "m_axi"), dut.clk, dut.rst, size=2**16)
@ -70,10 +70,10 @@ class TB(object):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
@ -171,7 +171,7 @@ async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
workers = []
for k in range(16):
workers.append(cocotb.fork(worker(tb.axi_master, k*0x1000, 0x1000, count=16)))
workers.append(cocotb.start_soon(worker(tb.axi_master, k*0x1000, 0x1000, count=16)))
while workers:
await workers.pop(0).join()

8
fpga/lib/axi/tb/axi_axil_adapter/test_axi_axil_adapter.py
View File

@ -45,7 +45,7 @@ class TB(object):
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.fork(Clock(dut.clk, 10, units="ns").start())
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
self.axi_master = AxiMaster(AxiBus.from_prefix(dut, "s_axi"), dut.clk, dut.rst)
self.axil_ram = AxiLiteRam(AxiLiteBus.from_prefix(dut, "m_axil"), dut.clk, dut.rst, size=2**16)
@ -70,10 +70,10 @@ class TB(object):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
@ -171,7 +171,7 @@ async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
workers = []
for k in range(16):
workers.append(cocotb.fork(worker(tb.axi_master, k*0x1000, 0x1000, count=16)))
workers.append(cocotb.start_soon(worker(tb.axi_master, k*0x1000, 0x1000, count=16)))
while workers:
await workers.pop(0).join()

8
fpga/lib/axi/tb/axi_cdma/test_axi_cdma.py
View File

@ -53,7 +53,7 @@ class TB(object):
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.fork(Clock(dut.clk, 10, units="ns").start())
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
# control interface
self.desc_source = DescSource(DescBus.from_prefix(dut, "s_axis_desc"), dut.clk, dut.rst)
@ -80,10 +80,10 @@ class TB(object):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
@ -103,7 +103,7 @@ async def run_test(dut, data_in=None, idle_inserter=None, backpressure_inserter=
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
dut.enable <= 1
dut.enable.value = 1
for length in list(range(1, byte_lanes*4+1))+[128]:
for read_offset in list(range(8, 8+byte_lanes*2, step_size))+list(range(4096-byte_lanes*2, 4096, step_size)):

8
fpga/lib/axi/tb/axi_crossbar/test_axi_crossbar.py
View File

@ -49,7 +49,7 @@ class TB(object):
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.fork(Clock(dut.clk, 10, units="ns").start())
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
self.axi_master = [AxiMaster(AxiBus.from_prefix(dut, f"s{k:02d}_axi"), dut.clk, dut.rst) for k in range(s_count)]
self.axi_ram = [AxiRam(AxiBus.from_prefix(dut, f"m{k:02d}_axi"), dut.clk, dut.rst, size=2**16) for k in range(m_count)]
@ -84,10 +84,10 @@ class TB(object):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
@ -188,7 +188,7 @@ async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
workers = []
for k in range(16):
workers.append(cocotb.fork(worker(tb.axi_master[k % len(tb.axi_master)], k*0x1000, 0x1000, count=16)))
workers.append(cocotb.start_soon(worker(tb.axi_master[k % len(tb.axi_master)], k*0x1000, 0x1000, count=16)))
while workers:
await workers.pop(0).join()

10
fpga/lib/axi/tb/axi_dma/test_axi_dma.py
View File

@ -57,7 +57,7 @@ class TB(object):
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.fork(Clock(dut.clk, 10, units="ns").start())
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
# read interface
self.read_desc_source = DescSource(DescBus.from_prefix(dut, "s_axis_read_desc"), dut.clk, dut.rst)
@ -95,10 +95,10 @@ class TB(object):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
@ -118,7 +118,7 @@ async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_ins
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
dut.write_enable <= 1
dut.write_enable.value = 1
for length in list(range(1, byte_lanes*4+1))+[128]:
for offset in list(range(0, byte_lanes*2, step_size))+list(range(4096-byte_lanes*2, 4096, step_size)):
@ -174,7 +174,7 @@ async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inse
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
dut.read_enable <= 1
dut.read_enable.value = 1
for length in list(range(1, byte_lanes*4+1))+[128]:
for offset in list(range(0, byte_lanes*2, step_size))+list(range(4096-byte_lanes*2, 4096, step_size)):

8
fpga/lib/axi/tb/axi_dma_rd/test_axi_dma_rd.py
View File

@ -56,7 +56,7 @@ class TB(object):
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.fork(Clock(dut.clk, 10, units="ns").start())
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
# read interface
self.read_desc_source = DescSource(DescBus.from_prefix(dut, "s_axis_read_desc"), dut.clk, dut.rst)
@ -82,10 +82,10 @@ class TB(object):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
@ -105,7 +105,7 @@ async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inse
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
dut.enable <= 1
dut.enable.value = 1
for length in list(range(1, byte_lanes*4+1))+[128]:
for offset in list(range(0, byte_lanes*2, step_size))+list(range(4096-byte_lanes*2, 4096, step_size)):

8
fpga/lib/axi/tb/axi_dma_wr/test_axi_dma_wr.py
View File

@ -56,7 +56,7 @@ class TB(object):
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.fork(Clock(dut.clk, 10, units="ns").start())
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
# write interface
self.write_desc_source = DescSource(DescBus.from_prefix(dut, "s_axis_write_desc"), dut.clk, dut.rst)
@ -83,10 +83,10 @@ class TB(object):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
@ -106,7 +106,7 @@ async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_ins
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
dut.enable <= 1
dut.enable.value = 1
for length in list(range(1, byte_lanes*4+1))+[128]:
for offset in list(range(0, byte_lanes*2, step_size))+list(range(4096-byte_lanes*2, 4096, step_size)):

18
fpga/lib/axi/tb/axi_dp_ram/test_axi_dp_ram.py
View File

@ -45,8 +45,8 @@ class TB(object):
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.fork(Clock(dut.a_clk, 8, units="ns").start())
cocotb.fork(Clock(dut.b_clk, 10, units="ns").start())
cocotb.start_soon(Clock(dut.a_clk, 8, units="ns").start())
cocotb.start_soon(Clock(dut.b_clk, 10, units="ns").start())
self.axi_master = []
@ -71,13 +71,13 @@ class TB(object):
self.dut.b_rst.setimmediatevalue(0)
await RisingEdge(self.dut.a_clk)
await RisingEdge(self.dut.a_clk)
self.dut.a_rst <= 1
self.dut.b_rst <= 1
self.dut.a_rst.value = 1
self.dut.b_rst.value = 1
await RisingEdge(self.dut.a_clk)
await RisingEdge(self.dut.a_clk)
self.dut.a_rst <= 0
self.dut.a_rst.value = 0
await RisingEdge(self.dut.b_clk)
self.dut.b_rst <= 0
self.dut.b_rst.value = 0
await RisingEdge(self.dut.a_clk)
await RisingEdge(self.dut.a_clk)
@ -167,8 +167,8 @@ async def run_test_arb(dut, data_in=None, idle_inserter=None, backpressure_inser
workers = []
for k in range(10):
workers.append(cocotb.fork(worker(tb.axi_master[0], k*256)))
workers.append(cocotb.fork(worker(tb.axi_master[1], k*256)))
workers.append(cocotb.start_soon(worker(tb.axi_master[0], k*256)))
workers.append(cocotb.start_soon(worker(tb.axi_master[1], k*256)))
while workers:
await workers.pop(0).join()
@ -204,7 +204,7 @@ async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
workers = []
for k in range(16):
workers.append(cocotb.fork(worker(tb.axi_master[k % len(tb.axi_master)], k*0x1000, 0x1000, count=16)))
workers.append(cocotb.start_soon(worker(tb.axi_master[k % len(tb.axi_master)], k*0x1000, 0x1000, count=16)))
while workers:
await workers.pop(0).join()

8
fpga/lib/axi/tb/axi_fifo/test_axi_fifo.py
View File

@ -45,7 +45,7 @@ class TB(object):
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.fork(Clock(dut.clk, 10, units="ns").start())
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
self.axi_master = AxiMaster(AxiBus.from_prefix(dut, "s_axi"), dut.clk, dut.rst)
self.axi_ram = AxiRam(AxiBus.from_prefix(dut, "m_axi"), dut.clk, dut.rst, size=2**16)
@ -70,10 +70,10 @@ class TB(object):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
@ -172,7 +172,7 @@ async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
workers = []
for k in range(16):
workers.append(cocotb.fork(worker(tb.axi_master, k*0x1000, 0x1000, count=16)))
workers.append(cocotb.start_soon(worker(tb.axi_master, k*0x1000, 0x1000, count=16)))
while workers:
await workers.pop(0).join()

8
fpga/lib/axi/tb/axi_interconnect/test_axi_interconnect.py
View File

@ -49,7 +49,7 @@ class TB(object):
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.fork(Clock(dut.clk, 10, units="ns").start())
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
self.axi_master = [AxiMaster(AxiBus.from_prefix(dut, f"s{k:02d}_axi"), dut.clk, dut.rst) for k in range(s_count)]
self.axi_ram = [AxiRam(AxiBus.from_prefix(dut, f"m{k:02d}_axi"), dut.clk, dut.rst, size=2**16) for k in range(m_count)]
@ -78,10 +78,10 @@ class TB(object):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
@ -182,7 +182,7 @@ async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
workers = []
for k in range(16):
workers.append(cocotb.fork(worker(tb.axi_master[k % len(tb.axi_master)], k*0x1000, 0x1000, count=16)))
workers.append(cocotb.start_soon(worker(tb.axi_master[k % len(tb.axi_master)], k*0x1000, 0x1000, count=16)))
while workers:
await workers.pop(0).join()

8
fpga/lib/axi/tb/axi_ram/test_axi_ram.py
View File

@ -45,7 +45,7 @@ class TB(object):
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.fork(Clock(dut.clk, 10, units="ns").start())
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
self.axi_master = AxiMaster(AxiBus.from_prefix(dut, "s_axi"), dut.clk, dut.rst)
@ -64,10 +64,10 @@ class TB(object):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
@ -163,7 +163,7 @@ async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
workers = []
for k in range(16):
workers.append(cocotb.fork(worker(tb.axi_master, k*0x1000, 0x1000, count=16)))
workers.append(cocotb.start_soon(worker(tb.axi_master, k*0x1000, 0x1000, count=16)))
while workers:
await workers.pop(0).join()

8
fpga/lib/axi/tb/axi_register/test_axi_register.py
View File

@ -45,7 +45,7 @@ class TB(object):
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.fork(Clock(dut.clk, 10, units="ns").start())
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
self.axi_master = AxiMaster(AxiBus.from_prefix(dut, "s_axi"), dut.clk, dut.rst)
self.axi_ram = AxiRam(AxiBus.from_prefix(dut, "m_axi"), dut.clk, dut.rst, size=2**16)
@ -70,10 +70,10 @@ class TB(object):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
@ -171,7 +171,7 @@ async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
workers = []
for k in range(16):
workers.append(cocotb.fork(worker(tb.axi_master, k*0x1000, 0x1000, count=16)))
workers.append(cocotb.start_soon(worker(tb.axi_master, k*0x1000, 0x1000, count=16)))
while workers:
await workers.pop(0).join()

8
fpga/lib/axi/tb/axil_adapter/test_axil_adapter.py
View File

@ -45,7 +45,7 @@ class TB(object):
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.fork(Clock(dut.clk, 10, units="ns").start())
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
self.axil_master = AxiLiteMaster(AxiLiteBus.from_prefix(dut, "s_axil"), dut.clk, dut.rst)
self.axil_ram = AxiLiteRam(AxiLiteBus.from_prefix(dut, "m_axil"), dut.clk, dut.rst, size=2**16)
@ -70,10 +70,10 @@ class TB(object):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
@ -163,7 +163,7 @@ async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
workers = []
for k in range(16):
workers.append(cocotb.fork(worker(tb.axil_master, k*0x1000, 0x1000, count=16)))
workers.append(cocotb.start_soon(worker(tb.axil_master, k*0x1000, 0x1000, count=16)))
while workers:
await workers.pop(0).join()

14
fpga/lib/axi/tb/axil_cdc/test_axil_cdc.py
View File

@ -45,8 +45,8 @@ class TB(object):
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.fork(Clock(dut.s_clk, 8, units="ns").start())
cocotb.fork(Clock(dut.m_clk, 10, units="ns").start())
cocotb.start_soon(Clock(dut.s_clk, 8, units="ns").start())
cocotb.start_soon(Clock(dut.m_clk, 10, units="ns").start())
self.axil_master = AxiLiteMaster(AxiLiteBus.from_prefix(dut, "s_axil"), dut.s_clk, dut.s_rst)
self.axil_ram = AxiLiteRam(AxiLiteBus.from_prefix(dut, "m_axil"), dut.m_clk, dut.m_rst, size=2**16)
@ -72,13 +72,13 @@ class TB(object):
self.dut.m_rst.setimmediatevalue(0)
await RisingEdge(self.dut.s_clk)
await RisingEdge(self.dut.s_clk)
self.dut.s_rst <= 1
self.dut.m_rst <= 1
self.dut.s_rst.value = 1
self.dut.m_rst.value = 1
await RisingEdge(self.dut.s_clk)
await RisingEdge(self.dut.s_clk)
self.dut.s_rst <= 0
self.dut.s_rst.value = 0
await RisingEdge(self.dut.m_clk)
self.dut.m_rst <= 0
self.dut.m_rst.value = 0
await RisingEdge(self.dut.s_clk)
await RisingEdge(self.dut.s_clk)
@ -168,7 +168,7 @@ async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
workers = []
for k in range(16):
workers.append(cocotb.fork(worker(tb.axil_master, k*0x1000, 0x1000, count=16)))
workers.append(cocotb.start_soon(worker(tb.axil_master, k*0x1000, 0x1000, count=16)))
while workers:
await workers.pop(0).join()

8
fpga/lib/axi/tb/axil_crossbar/test_axil_crossbar.py
View File

@ -49,7 +49,7 @@ class TB(object):
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.fork(Clock(dut.clk, 10, units="ns").start())
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
self.axil_master = [AxiLiteMaster(AxiLiteBus.from_prefix(dut, f"s{k:02d}_axil"), dut.clk, dut.rst) for k in range(s_count)]
self.axil_ram = [AxiLiteRam(AxiLiteBus.from_prefix(dut, f"m{k:02d}_axil"), dut.clk, dut.rst, size=2**16) for k in range(m_count)]
@ -78,10 +78,10 @@ class TB(object):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
@ -174,7 +174,7 @@ async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
workers = []
for k in range(16):
workers.append(cocotb.fork(worker(tb.axil_master[k % len(tb.axil_master)], k*0x1000, 0x1000, count=16)))
workers.append(cocotb.start_soon(worker(tb.axil_master[k % len(tb.axil_master)], k*0x1000, 0x1000, count=16)))
while workers:
await workers.pop(0).join()

18
fpga/lib/axi/tb/axil_dp_ram/test_axil_dp_ram.py
View File

@ -45,8 +45,8 @@ class TB(object):
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.fork(Clock(dut.a_clk, 8, units="ns").start())
cocotb.fork(Clock(dut.b_clk, 10, units="ns").start())
cocotb.start_soon(Clock(dut.a_clk, 8, units="ns").start())
cocotb.start_soon(Clock(dut.b_clk, 10, units="ns").start())
self.axil_master = []
@ -71,13 +71,13 @@ class TB(object):
self.dut.b_rst.setimmediatevalue(0)
await RisingEdge(self.dut.a_clk)
await RisingEdge(self.dut.a_clk)
self.dut.a_rst <= 1
self.dut.b_rst <= 1
self.dut.a_rst.value = 1
self.dut.b_rst.value = 1
await RisingEdge(self.dut.a_clk)
await RisingEdge(self.dut.a_clk)
self.dut.a_rst <= 0
self.dut.a_rst.value = 0
await RisingEdge(self.dut.b_clk)
self.dut.b_rst <= 0
self.dut.b_rst.value = 0
await RisingEdge(self.dut.a_clk)
await RisingEdge(self.dut.a_clk)
@ -159,8 +159,8 @@ async def run_test_arb(dut, data_in=None, idle_inserter=None, backpressure_inser
workers = []
for k in range(10):
workers.append(cocotb.fork(worker(tb.axil_master[0], k*256)))
workers.append(cocotb.fork(worker(tb.axil_master[1], k*256)))
workers.append(cocotb.start_soon(worker(tb.axil_master[0], k*256)))
workers.append(cocotb.start_soon(worker(tb.axil_master[1], k*256)))
while workers:
await workers.pop(0).join()
@ -196,7 +196,7 @@ async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
workers = []
for k in range(16):
workers.append(cocotb.fork(worker(tb.axil_master[k%len(tb.axil_master)], k*0x1000, 0x1000, count=16)))
workers.append(cocotb.start_soon(worker(tb.axil_master[k%len(tb.axil_master)], k*0x1000, 0x1000, count=16)))
while workers:
await workers.pop(0).join()

8
fpga/lib/axi/tb/axil_interconnect/test_axil_interconnect.py
View File

@ -49,7 +49,7 @@ class TB(object):
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.fork(Clock(dut.clk, 10, units="ns").start())
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
self.axil_master = [AxiLiteMaster(AxiLiteBus.from_prefix(dut, f"s{k:02d}_axil"), dut.clk, dut.rst) for k in range(s_count)]
self.axil_ram = [AxiLiteRam(AxiLiteBus.from_prefix(dut, f"m{k:02d}_axil"), dut.clk, dut.rst, size=2**16) for k in range(m_count)]
@ -78,10 +78,10 @@ class TB(object):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
@ -174,7 +174,7 @@ async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
workers = []
for k in range(16):
workers.append(cocotb.fork(worker(tb.axil_master[k % len(tb.axil_master)], k*0x1000, 0x1000, count=16)))
workers.append(cocotb.start_soon(worker(tb.axil_master[k % len(tb.axil_master)], k*0x1000, 0x1000, count=16)))
while workers:
await workers.pop(0).join()

8
fpga/lib/axi/tb/axil_ram/test_axil_ram.py
View File

@ -45,7 +45,7 @@ class TB(object):
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.fork(Clock(dut.clk, 10, units="ns").start())
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
self.axil_master = AxiLiteMaster(AxiLiteBus.from_prefix(dut, "s_axil"), dut.clk, dut.rst)
@ -64,10 +64,10 @@ class TB(object):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
@ -155,7 +155,7 @@ async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
workers = []
for k in range(16):
workers.append(cocotb.fork(worker(tb.axil_master, k*0x1000, 0x1000, count=16)))
workers.append(cocotb.start_soon(worker(tb.axil_master, k*0x1000, 0x1000, count=16)))
while workers:
await workers.pop(0).join()

36
fpga/lib/axi/tb/axil_reg_if/test_axil_reg_if.py
View File

@ -46,7 +46,7 @@ class TB(object):
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.fork(Clock(dut.clk, 10, units="ns").start())
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
self.axil_master = AxiLiteMaster(AxiLiteBus.from_prefix(dut, "s_axil"), dut.clk, dut.rst)
@ -58,8 +58,8 @@ class TB(object):
self.mem = mmap.mmap(-1, 16384)
cocotb.fork(self.run_reg_read())
cocotb.fork(self.run_reg_write())
cocotb.start_soon(self.run_reg_read())
cocotb.start_soon(self.run_reg_write())
def set_idle_generator(self, generator=None):
if generator:
@ -76,10 +76,10 @@ class TB(object):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
@ -87,15 +87,15 @@ class TB(object):
byte_lanes = len(self.dut.reg_wr_strb)
while True:
self.dut.reg_rd_data <= 0
self.dut.reg_rd_wait <= 0
self.dut.reg_rd_ack <= 0
self.dut.reg_rd_data.value = 0
self.dut.reg_rd_wait.value = 0
self.dut.reg_rd_ack.value = 0
await RisingEdge(self.dut.clk)
addr = (self.dut.reg_rd_addr.value.integer // byte_lanes) * byte_lanes
if self.dut.reg_rd_en.value.integer and addr < len(self.mem):
self.dut.reg_rd_wait <= 1
self.dut.reg_rd_wait.value = 1
for k in range(10):
await RisingEdge(self.dut.clk)
@ -104,17 +104,17 @@ class TB(object):
data = self.mem.read(byte_lanes)
self.dut.reg_rd_data <= int.from_bytes(data, 'little')
self.dut.reg_rd_wait <= 0
self.dut.reg_rd_ack <= 1
self.dut.reg_rd_data.value = int.from_bytes(data, 'little')
self.dut.reg_rd_wait.value = 0
self.dut.reg_rd_ack.value = 1
await RisingEdge(self.dut.clk)
async def run_reg_write(self):
byte_lanes = len(self.dut.reg_wr_strb)
while True:
self.dut.reg_wr_wait <= 0
self.dut.reg_wr_ack <= 0
self.dut.reg_wr_wait.value = 0
self.dut.reg_wr_ack.value = 0
await RisingEdge(self.dut.clk)
addr = (self.dut.reg_wr_addr.value.integer // byte_lanes) * byte_lanes
@ -122,7 +122,7 @@ class TB(object):
strb = self.dut.reg_wr_strb.value.integer
if self.dut.reg_wr_en.value.integer and addr < len(self.mem):
self.dut.reg_wr_wait <= 1
self.dut.reg_wr_wait.value = 1
for k in range(10):
await RisingEdge(self.dut.clk)
@ -137,8 +137,8 @@ class TB(object):
else:
self.mem.seek(1, 1)
self.dut.reg_wr_wait <= 0
self.dut.reg_wr_ack <= 1
self.dut.reg_wr_wait.value = 0
self.dut.reg_wr_ack.value = 1
await RisingEdge(self.dut.clk)
def mem_read(self, address, length):
@ -235,7 +235,7 @@ async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
workers = []
for k in range(16):
workers.append(cocotb.fork(worker(tb.axil_master, k*0x100, 0x100, count=16)))
workers.append(cocotb.start_soon(worker(tb.axil_master, k*0x100, 0x100, count=16)))
while workers:
await workers.pop(0).join()

8
fpga/lib/axi/tb/axil_register/test_axil_register.py
View File

@ -45,7 +45,7 @@ class TB(object):
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.fork(Clock(dut.clk, 10, units="ns").start())
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
self.axil_master = AxiLiteMaster(AxiLiteBus.from_prefix(dut, "s_axil"), dut.clk, dut.rst)
self.axil_ram = AxiLiteRam(AxiLiteBus.from_prefix(dut, "m_axil"), dut.clk, dut.rst, size=2**16)
@ -70,10 +70,10 @@ class TB(object):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
@ -163,7 +163,7 @@ async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
workers = []
for k in range(16):
workers.append(cocotb.fork(worker(tb.axil_master, k*0x1000, 0x1000, count=16)))
workers.append(cocotb.start_soon(worker(tb.axil_master, k*0x1000, 0x1000, count=16)))
while workers:
await workers.pop(0).join()