From f8a24d1c464f9581af06db9ad6a69abeb7488536 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sat, 6 Nov 2021 16:14:22 -0700 Subject: [PATCH] Add attributes to RAMs for proper synthesis in Quartus --- fpga/common/rtl/cpl_queue_manager.v | 3 +++ fpga/common/rtl/cpl_write.v | 3 +++ fpga/common/rtl/desc_fetch.v | 4 ++++ fpga/common/rtl/queue_manager.v | 3 +++ fpga/common/rtl/rx_engine.v | 14 ++++++++++++++ fpga/common/rtl/stats_collect.v | 1 + fpga/common/rtl/stats_counter.v | 1 + fpga/common/rtl/stats_dma_latency.v | 2 ++ fpga/common/rtl/tx_engine.v | 13 +++++++++++++ fpga/common/rtl/tx_scheduler_rr.v | 8 ++++++++ 10 files changed, 52 insertions(+) diff --git a/fpga/common/rtl/cpl_queue_manager.v b/fpga/common/rtl/cpl_queue_manager.v index 20d7dc585..752dfec43 100644 --- a/fpga/common/rtl/cpl_queue_manager.v +++ b/fpga/common/rtl/cpl_queue_manager.v @@ -222,6 +222,7 @@ reg s_axil_arready_reg = 0, s_axil_arready_next; reg [AXIL_DATA_WIDTH-1:0] s_axil_rdata_reg = 0, s_axil_rdata_next; reg s_axil_rvalid_reg = 0, s_axil_rvalid_next; +(* ramstyle = "no_rw_check" *) reg [QUEUE_RAM_WIDTH-1:0] queue_ram[QUEUE_COUNT-1:0]; reg [QUEUE_INDEX_WIDTH-1:0] queue_ram_read_ptr; reg [QUEUE_INDEX_WIDTH-1:0] queue_ram_write_ptr; @@ -243,7 +244,9 @@ wire [ADDR_WIDTH-1:0] queue_ram_read_data_base_addr = queue_ram_read_data_pipeli reg [OP_TABLE_SIZE-1:0] op_table_active = 0; reg [OP_TABLE_SIZE-1:0] op_table_commit = 0; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [QUEUE_INDEX_WIDTH-1:0] op_table_queue[OP_TABLE_SIZE-1:0]; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [QUEUE_PTR_WIDTH-1:0] op_table_queue_ptr[OP_TABLE_SIZE-1:0]; reg [CL_OP_TABLE_SIZE-1:0] op_table_start_ptr_reg = 0; reg [QUEUE_INDEX_WIDTH-1:0] op_table_start_queue; diff --git a/fpga/common/rtl/cpl_write.v b/fpga/common/rtl/cpl_write.v index 641e0598c..9591a34df 100644 --- a/fpga/common/rtl/cpl_write.v +++ b/fpga/common/rtl/cpl_write.v @@ -201,8 +201,11 @@ reg m_axis_dma_write_desc_valid_reg = 1'b0, m_axis_dma_write_desc_valid_next; reg [DESC_TABLE_SIZE-1:0] desc_table_active = 0; reg [DESC_TABLE_SIZE-1:0] desc_table_invalid = 0; reg [DESC_TABLE_SIZE-1:0] desc_table_cpl_write_done = 0; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [CL_PORTS-1:0] desc_table_sel[DESC_TABLE_SIZE-1:0]; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [REQ_TAG_WIDTH-1:0] desc_table_tag[DESC_TABLE_SIZE-1:0]; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [QUEUE_OP_TAG_WIDTH-1:0] desc_table_queue_op_tag[DESC_TABLE_SIZE-1:0]; reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_start_ptr_reg = 0; diff --git a/fpga/common/rtl/desc_fetch.v b/fpga/common/rtl/desc_fetch.v index 4c6f05a21..31eeb4a59 100644 --- a/fpga/common/rtl/desc_fetch.v +++ b/fpga/common/rtl/desc_fetch.v @@ -253,9 +253,13 @@ reg dec_active_2; reg [DESC_TABLE_SIZE-1:0] desc_table_active = 0; reg [DESC_TABLE_SIZE-1:0] desc_table_desc_fetched = 0; reg [DESC_TABLE_SIZE-1:0] desc_table_desc_read_done = 0; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [CL_PORTS-1:0] desc_table_sel[DESC_TABLE_SIZE-1:0]; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [LOG_BLOCK_SIZE_WIDTH-1:0] desc_table_log_desc_block_size[DESC_TABLE_SIZE-1:0]; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [REQ_TAG_WIDTH-1:0] desc_table_tag[DESC_TABLE_SIZE-1:0]; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [QUEUE_OP_TAG_WIDTH-1:0] desc_table_queue_op_tag[DESC_TABLE_SIZE-1:0]; reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_start_ptr_reg = 0; diff --git a/fpga/common/rtl/queue_manager.v b/fpga/common/rtl/queue_manager.v index be001519d..8ef89f881 100644 --- a/fpga/common/rtl/queue_manager.v +++ b/fpga/common/rtl/queue_manager.v @@ -224,6 +224,7 @@ reg s_axil_arready_reg = 0, s_axil_arready_next; reg [AXIL_DATA_WIDTH-1:0] s_axil_rdata_reg = 0, s_axil_rdata_next; reg s_axil_rvalid_reg = 0, s_axil_rvalid_next; +(* ramstyle = "no_rw_check" *) reg [QUEUE_RAM_WIDTH-1:0] queue_ram[QUEUE_COUNT-1:0]; reg [QUEUE_INDEX_WIDTH-1:0] queue_ram_read_ptr; reg [QUEUE_INDEX_WIDTH-1:0] queue_ram_write_ptr; @@ -244,7 +245,9 @@ wire [ADDR_WIDTH-1:0] queue_ram_read_data_base_addr = queue_ram_read_data_pipeli reg [OP_TABLE_SIZE-1:0] op_table_active = 0; reg [OP_TABLE_SIZE-1:0] op_table_commit = 0; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [QUEUE_INDEX_WIDTH-1:0] op_table_queue[OP_TABLE_SIZE-1:0]; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [QUEUE_PTR_WIDTH-1:0] op_table_queue_ptr[OP_TABLE_SIZE-1:0]; reg [CL_OP_TABLE_SIZE-1:0] op_table_start_ptr_reg = 0; reg [QUEUE_INDEX_WIDTH-1:0] op_table_start_queue; diff --git a/fpga/common/rtl/rx_engine.v b/fpga/common/rtl/rx_engine.v index b8a6e8018..052bd2a8f 100644 --- a/fpga/common/rtl/rx_engine.v +++ b/fpga/common/rtl/rx_engine.v @@ -315,19 +315,33 @@ reg [DESC_TABLE_SIZE-1:0] desc_table_invalid = 0; reg [DESC_TABLE_SIZE-1:0] desc_table_desc_fetched = 0; reg [DESC_TABLE_SIZE-1:0] desc_table_data_written = 0; reg [DESC_TABLE_SIZE-1:0] desc_table_cpl_write_done = 0; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [REQ_TAG_WIDTH-1:0] desc_table_tag[DESC_TABLE_SIZE-1:0]; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [QUEUE_INDEX_WIDTH-1:0] desc_table_queue[DESC_TABLE_SIZE-1:0]; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [QUEUE_PTR_WIDTH-1:0] desc_table_queue_ptr[DESC_TABLE_SIZE-1:0]; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [CPL_QUEUE_INDEX_WIDTH-1:0] desc_table_cpl_queue[DESC_TABLE_SIZE-1:0]; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [DMA_CLIENT_LEN_WIDTH-1:0] desc_table_dma_len[DESC_TABLE_SIZE-1:0]; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [DMA_CLIENT_LEN_WIDTH-1:0] desc_table_desc_len[DESC_TABLE_SIZE-1:0]; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [CL_RX_BUFFER_SIZE+1-1:0] desc_table_buf_ptr[DESC_TABLE_SIZE-1:0]; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [95:0] desc_table_ptp_ts[DESC_TABLE_SIZE-1:0]; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [31:0] desc_table_hash[DESC_TABLE_SIZE-1:0]; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [3:0] desc_table_hash_type[DESC_TABLE_SIZE-1:0]; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [15:0] desc_table_csum[DESC_TABLE_SIZE-1:0]; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg desc_table_read_commit[DESC_TABLE_SIZE-1:0]; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [DESC_TABLE_DMA_OP_COUNT_WIDTH-1:0] desc_table_write_count_start[DESC_TABLE_SIZE-1:0]; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [DESC_TABLE_DMA_OP_COUNT_WIDTH-1:0] desc_table_write_count_finish[DESC_TABLE_SIZE-1:0]; reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_start_ptr_reg = 0; diff --git a/fpga/common/rtl/stats_collect.v b/fpga/common/rtl/stats_collect.v index c99b17028..93e1a42ef 100644 --- a/fpga/common/rtl/stats_collect.v +++ b/fpga/common/rtl/stats_collect.v @@ -90,6 +90,7 @@ reg [COUNT-1:0] update_reg = {COUNT{1'b0}}, update_next; wire [ACC_WIDTH-1:0] acc_int[COUNT-1:0]; reg [COUNT-1:0] acc_clear; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [STAT_INC_WIDTH-1:0] mem_reg[COUNT-1:0]; reg [STAT_INC_WIDTH-1:0] mem_rd_data_reg = 0; diff --git a/fpga/common/rtl/stats_counter.v b/fpga/common/rtl/stats_counter.v index 3a45ea72e..c023a802d 100644 --- a/fpga/common/rtl/stats_counter.v +++ b/fpga/common/rtl/stats_counter.v @@ -122,6 +122,7 @@ reg [STAT_INC_WIDTH-1:0] inc_reg = {STAT_INC_WIDTH{1'b0}}, inc_next; reg rd_data_valid_reg = 1'b0, rd_data_valid_next; reg [WORD_SELECT_WIDTH-1:0] rd_data_shift_reg = 0, rd_data_shift_next; +(* ramstyle = "no_rw_check" *) reg [STAT_COUNT_WIDTH-1:0] mem_reg[(2**STAT_ID_WIDTH)-1:0]; reg [STAT_COUNT_WIDTH-1:0] mem_rd_data_reg = {STAT_COUNT_WIDTH{1'b0}}; diff --git a/fpga/common/rtl/stats_dma_latency.v b/fpga/common/rtl/stats_dma_latency.v index 9e1260fe8..981569807 100644 --- a/fpga/common/rtl/stats_dma_latency.v +++ b/fpga/common/rtl/stats_dma_latency.v @@ -80,7 +80,9 @@ assign out_status = out_status_reg; assign out_latency = out_latency_reg; assign out_valid = out_valid_reg; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [LEN_WIDTH-1:0] len_mem_reg[2**TAG_WIDTH-1:0]; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [COUNT_WIDTH-1:0] count_mem_reg[2**TAG_WIDTH-1:0]; integer i; diff --git a/fpga/common/rtl/tx_engine.v b/fpga/common/rtl/tx_engine.v index 3b1063339..19ab75677 100644 --- a/fpga/common/rtl/tx_engine.v +++ b/fpga/common/rtl/tx_engine.v @@ -317,18 +317,31 @@ reg [DESC_TABLE_SIZE-1:0] desc_table_desc_fetched = 0; reg [DESC_TABLE_SIZE-1:0] desc_table_data_fetched = 0; reg [DESC_TABLE_SIZE-1:0] desc_table_tx_done = 0; reg [DESC_TABLE_SIZE-1:0] desc_table_cpl_write_done = 0; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [REQ_TAG_WIDTH-1:0] desc_table_tag[DESC_TABLE_SIZE-1:0]; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [QUEUE_INDEX_WIDTH-1:0] desc_table_queue[DESC_TABLE_SIZE-1:0]; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [QUEUE_PTR_WIDTH-1:0] desc_table_queue_ptr[DESC_TABLE_SIZE-1:0]; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [CPL_QUEUE_INDEX_WIDTH-1:0] desc_table_cpl_queue[DESC_TABLE_SIZE-1:0]; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [6:0] desc_table_csum_start[DESC_TABLE_SIZE-1:0]; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [7:0] desc_table_csum_offset[DESC_TABLE_SIZE-1:0]; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg desc_table_csum_enable[DESC_TABLE_SIZE-1:0]; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [DMA_CLIENT_LEN_WIDTH-1:0] desc_table_len[DESC_TABLE_SIZE-1:0]; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [CL_TX_BUFFER_SIZE+1-1:0] desc_table_buf_ptr[DESC_TABLE_SIZE-1:0]; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [95:0] desc_table_ptp_ts[DESC_TABLE_SIZE-1:0]; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg desc_table_read_commit[DESC_TABLE_SIZE-1:0]; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [DESC_TABLE_DMA_OP_COUNT_WIDTH-1:0] desc_table_read_count_start[DESC_TABLE_SIZE-1:0]; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [DESC_TABLE_DMA_OP_COUNT_WIDTH-1:0] desc_table_read_count_finish[DESC_TABLE_SIZE-1:0]; reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_start_ptr_reg = 0; diff --git a/fpga/common/rtl/tx_scheduler_rr.v b/fpga/common/rtl/tx_scheduler_rr.v index f3ef46123..b8cf00bb9 100644 --- a/fpga/common/rtl/tx_scheduler_rr.v +++ b/fpga/common/rtl/tx_scheduler_rr.v @@ -195,6 +195,7 @@ reg s_axil_arready_reg = 0, s_axil_arready_next; reg [AXIL_DATA_WIDTH-1:0] s_axil_rdata_reg = 0, s_axil_rdata_next; reg s_axil_rvalid_reg = 0, s_axil_rvalid_next; +(* ramstyle = "no_rw_check" *) reg [QUEUE_RAM_WIDTH-1:0] queue_ram[QUEUE_COUNT-1:0]; reg [QUEUE_INDEX_WIDTH-1:0] queue_ram_read_ptr; reg [QUEUE_INDEX_WIDTH-1:0] queue_ram_write_ptr; @@ -212,10 +213,15 @@ wire queue_ram_read_data_scheduled = queue_ram_read_data_pipeline_reg[PIPELINE-1 wire [CL_OP_TABLE_SIZE-1:0] queue_ram_read_data_op_tail_index = queue_ram_read_data_pipeline_reg[PIPELINE-1][15:8]; reg [OP_TABLE_SIZE-1:0] op_table_active = 0; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [QUEUE_INDEX_WIDTH-1:0] op_table_queue[OP_TABLE_SIZE-1:0]; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg op_table_doorbell[OP_TABLE_SIZE-1:0]; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg op_table_is_head[OP_TABLE_SIZE-1:0]; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [CL_OP_TABLE_SIZE-1:0] op_table_next_index[OP_TABLE_SIZE-1:0]; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [CL_OP_TABLE_SIZE-1:0] op_table_prev_index[OP_TABLE_SIZE-1:0]; wire [CL_OP_TABLE_SIZE-1:0] op_table_start_ptr; wire op_table_start_ptr_valid; @@ -235,7 +241,9 @@ reg op_table_update_prev_en; reg [CL_OP_TABLE_SIZE+1-1:0] finish_fifo_wr_ptr_reg = 0, finish_fifo_wr_ptr_next; reg [CL_OP_TABLE_SIZE+1-1:0] finish_fifo_rd_ptr_reg = 0, finish_fifo_rd_ptr_next; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [REQ_TAG_WIDTH-1:0] finish_fifo_tag[(2**CL_OP_TABLE_SIZE)-1:0]; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg finish_fifo_status[(2**CL_OP_TABLE_SIZE)-1:0]; reg finish_fifo_we; reg [REQ_TAG_WIDTH-1:0] finish_fifo_wr_tag;