From f92c1ea980765e55aa39867c5bc277f267d31bea Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Thu, 28 Feb 2019 23:46:39 -0800 Subject: [PATCH] Reorder capability registrations --- tb/pcie_us.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tb/pcie_us.py b/tb/pcie_us.py index d7ec61e9e..c8821fc70 100644 --- a/tb/pcie_us.py +++ b/tb/pcie_us.py @@ -650,10 +650,10 @@ class UltrascalePCIeFunction(Endpoint, MSICapability, MSIXCapability): self.msi_64bit_address_capable = 1 self.msi_per_vector_mask_capable = 0 - self.register_capability(PCIE_CAP_ID, offset=48) - self.register_capability(MSIX_CAP_ID, offset=44) - self.register_capability(PM_CAP_ID, offset=32) - self.register_capability(MSI_CAP_ID, offset=36) + self.register_capability(PM_CAP_ID, offset=0x20) + self.register_capability(MSI_CAP_ID, offset=0x24) + self.register_capability(MSIX_CAP_ID, offset=0x2c) + self.register_capability(PCIE_CAP_ID, offset=0x30) class UltrascalePCIe(Device):