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Add TX and RX enable inputs to MACs

Browse Source 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-08-24 01:24:33 -07:00
parent 20c542051d
commit fa05d4ff3c
78 changed files with 310 additions and 72 deletions
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4
example/520N_MX/fpga_10g/rtl/fpga_core.v
View File

@ -497,7 +497,9 @@ eth_mac_10g_fifo_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.cfg_ifg(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
eth_axis_rx #(

4
example/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v
View File

@ -419,7 +419,9 @@ eth_mac_10g_fifo_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.cfg_ifg(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
eth_axis_rx #(

4
example/ATLYS/fpga/rtl/fpga_core.v
View File

@ -356,7 +356,9 @@ eth_mac_inst (
.rx_fifo_good_frame(),
.speed(),
.cfg_ifg(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
eth_axis_rx

4
example/AU200/fpga_25g/rtl/fpga_core.v
View File

@ -422,7 +422,9 @@ eth_mac_10g_fifo_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.cfg_ifg(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
eth_axis_rx #(

4
example/AU250/fpga_25g/rtl/fpga_core.v
View File

@ -422,7 +422,9 @@ eth_mac_10g_fifo_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.cfg_ifg(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
eth_axis_rx #(

4
example/AU280/fpga_25g/rtl/fpga_core.v
View File

@ -407,7 +407,9 @@ eth_mac_10g_fifo_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.cfg_ifg(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
eth_axis_rx #(

4
example/AU50/fpga_25g/rtl/fpga_core.v
View File

@ -374,7 +374,9 @@ eth_mac_10g_fifo_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.cfg_ifg(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
eth_axis_rx #(

4
example/Arty/fpga/rtl/fpga_core.v
View File

@ -363,7 +363,9 @@ eth_mac_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.cfg_ifg(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
eth_axis_rx

4
example/C10LP/fpga/rtl/fpga_core.v
View File

@ -340,7 +340,9 @@ eth_mac_inst (
.rx_fifo_good_frame(),
.speed(),
.cfg_ifg(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
eth_axis_rx

4
example/DE2-115/fpga/rtl/fpga_core.v
View File

@ -448,7 +448,9 @@ eth_mac_inst (
.rx_fifo_good_frame(),
.speed(),
.cfg_ifg(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
eth_axis_rx

4
example/DE5-Net/fpga/rtl/fpga_core.v
View File

@ -372,7 +372,9 @@ eth_mac_10g_fifo_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.cfg_ifg(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
eth_axis_rx #(

4
example/ExaNIC_X10/fpga/rtl/fpga_core.v
View File

@ -352,7 +352,9 @@ eth_mac_10g_fifo_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.cfg_ifg(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
eth_axis_rx #(

4
example/ExaNIC_X25/fpga_25g/rtl/fpga_core.v
View File

@ -352,7 +352,9 @@ eth_mac_10g_fifo_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.cfg_ifg(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
eth_axis_rx #(

4
example/HTG640/fpga/rtl/fpga_core.v
View File

@ -516,7 +516,9 @@ eth_mac_10g_fifo_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.cfg_ifg(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
eth_axis_rx #(

4
example/HTG640/fpga_cxpt16/rtl/fpga_core.v
View File

@ -308,7 +308,9 @@ eth_mac_fifo_inst (
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.cfg_ifg(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b0),
.cfg_rx_enable(1'b1)
);
eth_axis_rx #(

4
example/HTG9200/fpga_25g/rtl/fpga_core.v
View File

@ -715,7 +715,9 @@ eth_mac_10g_fifo_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.cfg_ifg(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
eth_axis_rx #(

4
example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/fpga_core.v
View File

@ -967,7 +967,9 @@ eth_mac_10g_fifo_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.cfg_ifg(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
eth_axis_rx #(

4
example/KC705/fpga_gmii/rtl/fpga_core.v
View File

@ -360,7 +360,9 @@ eth_mac_inst (
.rx_fifo_good_frame(),
.speed(),
.cfg_ifg(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
eth_axis_rx

4
example/KC705/fpga_rgmii/rtl/fpga_core.v
View File

@ -357,7 +357,9 @@ eth_mac_inst (
.rx_fifo_good_frame(),
.speed(),
.cfg_ifg(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
eth_axis_rx

4
example/KC705/fpga_sgmii/rtl/fpga_core.v
View File

@ -357,7 +357,9 @@ eth_mac_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.cfg_ifg(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
eth_axis_rx

4
example/ML605/fpga_gmii/rtl/fpga_core.v
View File

@ -369,7 +369,9 @@ eth_mac_inst (
.rx_fifo_good_frame(),
.speed(),
.cfg_ifg(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
eth_axis_rx

4
example/ML605/fpga_rgmii/rtl/fpga_core.v
View File

@ -366,7 +366,9 @@ eth_mac_inst (
.rx_fifo_good_frame(),
.speed(),
.cfg_ifg(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
eth_axis_rx

4
example/ML605/fpga_sgmii/rtl/fpga_core.v
View File

@ -366,7 +366,9 @@ eth_mac_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.cfg_ifg(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
eth_axis_rx

4
example/NetFPGA_SUME/fpga/rtl/fpga_core.v
View File

@ -385,7 +385,9 @@ eth_mac_10g_fifo_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.cfg_ifg(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
eth_axis_rx #(

4
example/NexysVideo/fpga/rtl/fpga_core.v
View File

@ -355,7 +355,9 @@ eth_mac_inst (
.rx_fifo_good_frame(),
.speed(),
.cfg_ifg(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
eth_axis_rx

4
example/RV901T/fpga/rtl/fpga_core.v
View File

@ -344,7 +344,9 @@ eth_mac_inst (
.rx_fifo_good_frame(),
.speed(),
.cfg_ifg(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
assign phy_1_tx_clk = 1'b0;

4
example/S10MX_DK/fpga_10g/rtl/fpga_core.v
View File

@ -411,7 +411,9 @@ eth_mac_10g_fifo_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.cfg_ifg(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
eth_axis_rx #(

8
example/VCU108/fpga_10g/rtl/fpga_core.v
View File

@ -418,7 +418,9 @@ eth_mac_10g_fifo_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.cfg_ifg(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
// 1G interface for debugging
@ -497,7 +499,9 @@ eth_mac_1g_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.cfg_ifg(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
axis_adapter #(

4
example/VCU108/fpga_1g/rtl/fpga_core.v
View File

@ -357,7 +357,9 @@ eth_mac_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.cfg_ifg(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
eth_axis_rx

4
example/VCU118/fpga_1g/rtl/fpga_core.v
View File

@ -357,7 +357,9 @@ eth_mac_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.cfg_ifg(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
eth_axis_rx

8
example/VCU118/fpga_25g/rtl/fpga_core.v
View File

@ -459,7 +459,9 @@ eth_mac_10g_fifo_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.cfg_ifg(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
// 1G interface for debugging
@ -538,7 +540,9 @@ eth_mac_1g_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.cfg_ifg(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
axis_adapter #(

8
example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/fpga_core.v
View File

@ -709,7 +709,9 @@ eth_mac_10g_fifo_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.cfg_ifg(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
// 1G interface for debugging
@ -788,7 +790,9 @@ eth_mac_1g_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.cfg_ifg(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
axis_adapter #(

4
example/VCU1525/fpga_25g/rtl/fpga_core.v
View File

@ -422,7 +422,9 @@ eth_mac_10g_fifo_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.cfg_ifg(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
eth_axis_rx #(

4
example/ZCU102/fpga/rtl/fpga_core.v
View File

@ -384,7 +384,9 @@ eth_mac_10g_fifo_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.cfg_ifg(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
eth_axis_rx #(

4
example/ZCU106/fpga/rtl/fpga_core.v
View File

@ -364,7 +364,9 @@ eth_mac_10g_fifo_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.cfg_ifg(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
eth_axis_rx #(

4
example/fb2CG/fpga_25g/rtl/fpga_core.v
View File

@ -420,7 +420,9 @@ eth_mac_10g_fifo_inst (
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.cfg_ifg(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
eth_axis_rx #(

7
rtl/axis_baser_rx_64.v
View File

@ -66,6 +66,11 @@ module axis_baser_rx_64 #
*/
input wire [PTP_TS_WIDTH-1:0] ptp_ts,
/*
* Configuration
*/
input wire cfg_rx_enable,
/*
* Status
*/
@ -285,7 +290,7 @@ always @* begin
m_axis_tuser_next[1 +: PTP_TS_WIDTH] = (PTP_TS_WIDTH != 96 || ptp_ts_borrow_reg) ? ptp_ts_reg : ptp_ts_adj_reg;
end
if (input_type_d1 == INPUT_TYPE_START_0) begin
if (input_type_d1 == INPUT_TYPE_START_0 && cfg_rx_enable) begin
// start condition
reset_crc = 1'b0;
state_next = STATE_PAYLOAD;

3
rtl/axis_baser_tx_64.v
View File

@ -80,6 +80,7 @@ module axis_baser_tx_64 #
* Configuration
*/
input wire [7:0] cfg_ifg,
input wire cfg_tx_enable,
/*
* Status
@ -397,7 +398,7 @@ always @* begin
s_tdata_next = s_axis_tdata_masked;
s_empty_next = keep2empty(s_axis_tkeep);
if (s_axis_tvalid) begin
if (s_axis_tvalid && cfg_tx_enable) begin
// XGMII start and preamble
if (swap_lanes_reg) begin
// lanes swapped

7
rtl/axis_gmii_rx.v
View File

@ -68,6 +68,11 @@ module axis_gmii_rx #
input wire clk_enable,
input wire mii_select,
/*
* Configuration
*/
input wire cfg_rx_enable,
/*
* Status
*/
@ -186,7 +191,7 @@ always @* begin
// idle state - wait for packet
reset_crc = 1'b1;
if (gmii_rx_dv_d4 && !gmii_rx_er_d4 && gmii_rxd_d4 == ETH_SFD) begin
if (gmii_rx_dv_d4 && !gmii_rx_er_d4 && gmii_rxd_d4 == ETH_SFD && cfg_rx_enable) begin
state_next = STATE_PAYLOAD;
end else begin
state_next = STATE_IDLE;

3
rtl/axis_gmii_tx.v
View File

@ -81,6 +81,7 @@ module axis_gmii_tx #
* Configuration
*/
input wire [7:0] cfg_ifg,
input wire cfg_tx_enable,
/*
* Status
@ -240,7 +241,7 @@ always @* begin
frame_min_count_next = MIN_FRAME_LENGTH-4-1;
if (s_axis_tvalid) begin
if (s_axis_tvalid && cfg_tx_enable) begin
mii_odd_next = 1'b1;
gmii_txd_next = ETH_PRE;
gmii_tx_en_next = 1'b1;

7
rtl/axis_xgmii_rx_32.v
View File

@ -64,6 +64,11 @@ module axis_xgmii_rx_32 #
*/
input wire [PTP_TS_WIDTH-1:0] ptp_ts,
/*
* Configuration
*/
input wire cfg_rx_enable,
/*
* Status
*/
@ -244,7 +249,7 @@ always @* begin
// idle state - wait for packet
reset_crc = 1'b1;
if (xgmii_start_d2) begin
if (xgmii_start_d2 && cfg_rx_enable) begin
// start condition
if (control_masked) begin
// control or error characters in first data word

7
rtl/axis_xgmii_rx_64.v
View File

@ -66,6 +66,11 @@ module axis_xgmii_rx_64 #
*/
input wire [PTP_TS_WIDTH-1:0] ptp_ts,
/*
* Configuration
*/
input wire cfg_rx_enable,
/*
* Status
*/
@ -270,7 +275,7 @@ always @* begin
// idle state - wait for packet
reset_crc = 1'b1;
if (xgmii_start_d1) begin
if (xgmii_start_d1 && cfg_rx_enable) begin
// start condition
if (PTP_TS_ENABLE) begin

3
rtl/axis_xgmii_tx_32.v
View File

@ -78,6 +78,7 @@ module axis_xgmii_tx_32 #
* Configuration
*/
input wire [7:0] cfg_ifg,
input wire cfg_tx_enable,
/*
* Status
@ -308,7 +309,7 @@ always @* begin
s_tdata_next = s_axis_tdata_masked;
s_empty_next = keep2empty(s_axis_tkeep);
if (s_axis_tvalid) begin
if (s_axis_tvalid && cfg_tx_enable) begin
// XGMII start and preamble
xgmii_txd_next = {{3{ETH_PRE}}, XGMII_START};
xgmii_txc_next = 4'b0001;

17
rtl/axis_xgmii_tx_64.v
View File

@ -80,6 +80,7 @@ module axis_xgmii_tx_64 #
* Configuration
*/
input wire [7:0] cfg_ifg,
input wire cfg_tx_enable,
/*
* Status
@ -335,7 +336,7 @@ always @* begin
// idle state - wait for data
frame_min_count_next = MIN_FRAME_LENGTH-4-CTRL_WIDTH;
reset_crc = 1'b1;
s_axis_tready_next = 1'b1;
s_axis_tready_next = cfg_tx_enable;
// XGMII idle
xgmii_txd_next = {CTRL_WIDTH{XGMII_IDLE}};
@ -344,7 +345,7 @@ always @* begin
s_tdata_next = s_axis_tdata_masked;
s_empty_next = keep2empty(s_axis_tkeep);
if (s_axis_tvalid) begin
if (s_axis_tvalid && s_axis_tready) begin
// XGMII start and preamble
if (swap_lanes_reg) begin
// lanes swapped
@ -505,14 +506,14 @@ always @* begin
ifg_count_next = 8'd0;
swap_lanes_next = 1'b0;
end
s_axis_tready_next = 1'b1;
s_axis_tready_next = cfg_tx_enable;
state_next = STATE_IDLE;
end
end else begin
if (ifg_count_next > 8'd4) begin
state_next = STATE_IFG;
end else begin
s_axis_tready_next = 1'b1;
s_axis_tready_next = cfg_tx_enable;
swap_lanes_next = ifg_count_next != 0;
state_next = STATE_IDLE;
end
@ -538,14 +539,14 @@ always @* begin
ifg_count_next = 8'd0;
swap_lanes_next = 1'b0;
end
s_axis_tready_next = 1'b1;
s_axis_tready_next = cfg_tx_enable;
state_next = STATE_IDLE;
end
end else begin
if (ifg_count_next > 8'd4) begin
state_next = STATE_IFG;
end else begin
s_axis_tready_next = 1'b1;
s_axis_tready_next = cfg_tx_enable;
swap_lanes_next = ifg_count_next != 0;
state_next = STATE_IDLE;
end
@ -577,14 +578,14 @@ always @* begin
ifg_count_next = 8'd0;
swap_lanes_next = 1'b0;
end
s_axis_tready_next = 1'b1;
s_axis_tready_next = cfg_tx_enable;
state_next = STATE_IDLE;
end
end else begin
if (ifg_count_next > 8'd4) begin
state_next = STATE_IFG;
end else begin
s_axis_tready_next = 1'b1;
s_axis_tready_next = cfg_tx_enable;
swap_lanes_next = ifg_count_next != 0;
state_next = STATE_IDLE;
end

6
rtl/eth_mac_10g.v
View File

@ -151,6 +151,8 @@ module eth_mac_10g #
* Configuration
*/
input wire [7:0] cfg_ifg,
input wire cfg_tx_enable,
input wire cfg_rx_enable,
input wire [47:0] cfg_mcf_rx_eth_dst_mcast,
input wire cfg_mcf_rx_check_eth_dst_mcast,
input wire [47:0] cfg_mcf_rx_eth_dst_ucast,
@ -238,6 +240,7 @@ axis_xgmii_rx_inst (
.m_axis_tlast(rx_axis_tlast_int),
.m_axis_tuser(rx_axis_tuser_int),
.ptp_ts(rx_ptp_ts),
.cfg_rx_enable(cfg_rx_enable),
.start_packet(rx_start_packet),
.error_bad_frame(rx_error_bad_frame),
.error_bad_fcs(rx_error_bad_fcs)
@ -275,6 +278,7 @@ axis_xgmii_tx_inst (
.m_axis_ptp_ts_tag(tx_axis_ptp_ts_tag),
.m_axis_ptp_ts_valid(tx_axis_ptp_ts_valid),
.cfg_ifg(cfg_ifg),
.cfg_tx_enable(cfg_tx_enable),
.start_packet(tx_start_packet),
.error_underflow(tx_error_underflow)
);
@ -300,6 +304,7 @@ axis_xgmii_rx_inst (
.m_axis_tlast(rx_axis_tlast_int),
.m_axis_tuser(rx_axis_tuser_int),
.ptp_ts(rx_ptp_ts),
.cfg_rx_enable(cfg_rx_enable),
.start_packet(rx_start_packet[0]),
.error_bad_frame(rx_error_bad_frame),
.error_bad_fcs(rx_error_bad_fcs)
@ -337,6 +342,7 @@ axis_xgmii_tx_inst (
.m_axis_ptp_ts_tag(tx_axis_ptp_ts_tag),
.m_axis_ptp_ts_valid(tx_axis_ptp_ts_valid),
.cfg_ifg(cfg_ifg),
.cfg_tx_enable(cfg_tx_enable),
.start_packet(tx_start_packet[0]),
.error_underflow(tx_error_underflow)
);

8
rtl/eth_mac_10g_fifo.v
View File

@ -133,7 +133,9 @@ module eth_mac_10g_fifo #
/*
* Configuration
*/
input wire [7:0] cfg_ifg
input wire [7:0] cfg_ifg,
input wire cfg_tx_enable,
input wire cfg_rx_enable
);
parameter KEEP_WIDTH = DATA_WIDTH/8;
@ -382,7 +384,9 @@ eth_mac_10g_inst (
.rx_error_bad_frame(rx_error_bad_frame_int),
.rx_error_bad_fcs(rx_error_bad_fcs_int),
.cfg_ifg(cfg_ifg)
.cfg_ifg(cfg_ifg),
.cfg_tx_enable(cfg_tx_enable),
.cfg_rx_enable(cfg_rx_enable)
);
axis_async_fifo_adapter #(

4
rtl/eth_mac_1g.v
View File

@ -154,6 +154,8 @@ module eth_mac_1g #
* Configuration
*/
input wire [7:0] cfg_ifg,
input wire cfg_tx_enable,
input wire cfg_rx_enable,
input wire [47:0] cfg_mcf_rx_eth_dst_mcast,
input wire cfg_mcf_rx_check_eth_dst_mcast,
input wire [47:0] cfg_mcf_rx_eth_dst_ucast,
@ -220,6 +222,7 @@ axis_gmii_rx_inst (
.ptp_ts(rx_ptp_ts),
.clk_enable(rx_clk_enable),
.mii_select(rx_mii_select),
.cfg_rx_enable(cfg_rx_enable),
.start_packet(rx_start_packet),
.error_bad_frame(rx_error_bad_frame),
.error_bad_fcs(rx_error_bad_fcs)
@ -254,6 +257,7 @@ axis_gmii_tx_inst (
.clk_enable(tx_clk_enable),
.mii_select(tx_mii_select),
.cfg_ifg(cfg_ifg),
.cfg_tx_enable(cfg_tx_enable),
.start_packet(tx_start_packet),
.error_underflow(tx_error_underflow)
);

8
rtl/eth_mac_1g_fifo.v
View File

@ -113,7 +113,9 @@ module eth_mac_1g_fifo #
/*
* Configuration
*/
input wire [7:0] cfg_ifg
input wire [7:0] cfg_ifg,
input wire cfg_tx_enable,
input wire cfg_rx_enable
);
wire [7:0] tx_fifo_axis_tdata;
@ -219,7 +221,9 @@ eth_mac_1g_inst (
.tx_error_underflow(tx_error_underflow_int),
.rx_error_bad_frame(rx_error_bad_frame_int),
.rx_error_bad_fcs(rx_error_bad_fcs_int),
.cfg_ifg(cfg_ifg)
.cfg_ifg(cfg_ifg),
.cfg_tx_enable(cfg_tx_enable),
.cfg_rx_enable(cfg_rx_enable)
);
axis_async_fifo_adapter #(

8
rtl/eth_mac_1g_gmii.v
View File

@ -96,7 +96,9 @@ module eth_mac_1g_gmii #
/*
* Configuration
*/
input wire [7:0] cfg_ifg
input wire [7:0] cfg_ifg,
input wire cfg_tx_enable,
input wire cfg_rx_enable
);
wire [7:0] mac_gmii_rxd;
@ -244,7 +246,9 @@ eth_mac_1g_inst (
.tx_error_underflow(tx_error_underflow),
.rx_error_bad_frame(rx_error_bad_frame),
.rx_error_bad_fcs(rx_error_bad_fcs),
.cfg_ifg(cfg_ifg)
.cfg_ifg(cfg_ifg),
.cfg_tx_enable(cfg_tx_enable),
.cfg_rx_enable(cfg_rx_enable)
);
endmodule

8
rtl/eth_mac_1g_gmii_fifo.v
View File

@ -118,7 +118,9 @@ module eth_mac_1g_gmii_fifo #
/*
* Configuration
*/
input wire [7:0] cfg_ifg
input wire [7:0] cfg_ifg,
input wire cfg_tx_enable,
input wire cfg_rx_enable
);
wire tx_clk;
@ -246,7 +248,9 @@ eth_mac_1g_gmii_inst (
.rx_error_bad_frame(rx_error_bad_frame_int),
.rx_error_bad_fcs(rx_error_bad_fcs_int),
.speed(speed_int),
.cfg_ifg(cfg_ifg)
.cfg_ifg(cfg_ifg),
.cfg_tx_enable(cfg_tx_enable),
.cfg_rx_enable(cfg_rx_enable)
);
axis_async_fifo_adapter #(

8
rtl/eth_mac_1g_rgmii.v
View File

@ -95,7 +95,9 @@ module eth_mac_1g_rgmii #
/*
* Configuration
*/
input wire [7:0] cfg_ifg
input wire [7:0] cfg_ifg,
input wire cfg_tx_enable,
input wire cfg_rx_enable
);
wire [7:0] mac_gmii_rxd;
@ -244,7 +246,9 @@ eth_mac_1g_inst (
.tx_error_underflow(tx_error_underflow),
.rx_error_bad_frame(rx_error_bad_frame),
.rx_error_bad_fcs(rx_error_bad_fcs),
.cfg_ifg(cfg_ifg)
.cfg_ifg(cfg_ifg),
.cfg_tx_enable(cfg_tx_enable),
.cfg_rx_enable(cfg_rx_enable)
);
endmodule

8
rtl/eth_mac_1g_rgmii_fifo.v
View File

@ -117,7 +117,9 @@ module eth_mac_1g_rgmii_fifo #
/*
* Configuration
*/
input wire [7:0] cfg_ifg
input wire [7:0] cfg_ifg,
input wire cfg_tx_enable,
input wire cfg_rx_enable
);
wire tx_clk;
@ -244,7 +246,9 @@ eth_mac_1g_rgmii_inst (
.rx_error_bad_frame(rx_error_bad_frame_int),
.rx_error_bad_fcs(rx_error_bad_fcs_int),
.speed(speed_int),
.cfg_ifg(cfg_ifg)
.cfg_ifg(cfg_ifg),
.cfg_tx_enable(cfg_tx_enable),
.cfg_rx_enable(cfg_rx_enable)
);
axis_async_fifo_adapter #(

8
rtl/eth_mac_mii.v
View File

@ -91,7 +91,9 @@ module eth_mac_mii #
/*
* Configuration
*/
input wire [7:0] cfg_ifg
input wire [7:0] cfg_ifg,
input wire cfg_tx_enable,
input wire cfg_rx_enable
);
wire [3:0] mac_mii_rxd;
@ -162,7 +164,9 @@ eth_mac_1g_inst (
.rx_start_packet(rx_start_packet),
.rx_error_bad_frame(rx_error_bad_frame),
.rx_error_bad_fcs(rx_error_bad_fcs),
.cfg_ifg(cfg_ifg)
.cfg_ifg(cfg_ifg),
.cfg_tx_enable(cfg_tx_enable),
.cfg_rx_enable(cfg_rx_enable)
);
endmodule

8
rtl/eth_mac_mii_fifo.v
View File

@ -111,7 +111,9 @@ module eth_mac_mii_fifo #
/*
* Configuration
*/
input wire [7:0] cfg_ifg
input wire [7:0] cfg_ifg,
input wire cfg_tx_enable,
input wire cfg_rx_enable
);
wire tx_clk;
@ -223,7 +225,9 @@ eth_mac_1g_mii_inst (
.tx_error_underflow(tx_error_underflow_int),
.rx_error_bad_frame(rx_error_bad_frame_int),
.rx_error_bad_fcs(rx_error_bad_fcs_int),
.cfg_ifg(cfg_ifg)
.cfg_ifg(cfg_ifg),
.cfg_tx_enable(cfg_tx_enable),
.cfg_rx_enable(cfg_rx_enable)
);
axis_async_fifo_adapter #(

4
rtl/eth_mac_phy_10g.v
View File

@ -121,6 +121,8 @@ module eth_mac_phy_10g #
* Configuration
*/
input wire [7:0] cfg_ifg,
input wire cfg_tx_enable,
input wire cfg_rx_enable,
input wire cfg_tx_prbs31_enable,
input wire cfg_rx_prbs31_enable
);
@ -163,6 +165,7 @@ eth_mac_phy_10g_rx_inst (
.rx_block_lock(rx_block_lock),
.rx_high_ber(rx_high_ber),
.rx_status(rx_status),
.cfg_rx_enable(cfg_rx_enable),
.cfg_rx_prbs31_enable(cfg_rx_prbs31_enable)
);
@ -204,6 +207,7 @@ eth_mac_phy_10g_tx_inst (
.tx_start_packet(tx_start_packet),
.tx_error_underflow(tx_error_underflow),
.cfg_ifg(cfg_ifg),
.cfg_tx_enable(cfg_tx_enable),
.cfg_tx_prbs31_enable(cfg_tx_prbs31_enable)
);

4
rtl/eth_mac_phy_10g_fifo.v
View File

@ -148,6 +148,8 @@ module eth_mac_phy_10g_fifo #
* Configuration
*/
input wire [7:0] cfg_ifg,
input wire cfg_tx_enable,
input wire cfg_rx_enable,
input wire cfg_tx_prbs31_enable,
input wire cfg_rx_prbs31_enable
);
@ -426,6 +428,8 @@ eth_mac_phy_10g_inst (
.rx_status(rx_status_int),
.cfg_ifg(cfg_ifg),
.cfg_tx_enable(cfg_tx_enable),
.cfg_rx_enable(cfg_rx_enable),
.cfg_tx_prbs31_enable(cfg_tx_prbs31_enable),
.cfg_rx_prbs31_enable(cfg_rx_prbs31_enable)

4
rtl/eth_mac_phy_10g_rx.v
View File

@ -90,6 +90,7 @@ module eth_mac_phy_10g_rx #
/*
* Configuration
*/
input wire cfg_rx_enable,
input wire cfg_rx_prbs31_enable
);
@ -165,7 +166,8 @@ axis_baser_rx_inst (
.start_packet(rx_start_packet),
.error_bad_frame(rx_error_bad_frame),
.error_bad_fcs(rx_error_bad_fcs),
.rx_bad_block(rx_bad_block)
.rx_bad_block(rx_bad_block),
.cfg_rx_enable(cfg_rx_enable)
);
endmodule

4
rtl/eth_mac_phy_10g_tx.v
View File

@ -90,6 +90,7 @@ module eth_mac_phy_10g_tx #
* Configuration
*/
input wire [7:0] cfg_ifg,
input wire cfg_tx_enable,
input wire cfg_tx_prbs31_enable
);
@ -147,7 +148,8 @@ axis_baser_tx_inst (
.m_axis_ptp_ts_valid(m_axis_ptp_ts_valid),
.start_packet(tx_start_packet),
.error_underflow(tx_error_underflow),
.cfg_ifg(cfg_ifg)
.cfg_ifg(cfg_ifg),
.cfg_tx_enable(cfg_tx_enable)
);
eth_phy_10g_tx_if #(

3
tb/axis_baser_rx_64/test_axis_baser_rx_64.py
View File

@ -64,6 +64,8 @@ class TB:
self.ptp_clock = PtpClockSimTime(ts_64=dut.ptp_ts, clock=dut.clk)
dut.cfg_rx_enable.setimmediatevalue(0)
async def reset(self):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
@ -81,6 +83,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12):
tb = TB(dut)
tb.source.ifg = ifg
tb.dut.cfg_rx_enable.value = 1
await tb.reset()

3
tb/axis_baser_tx_64/test_axis_baser_tx_64.py
View File

@ -74,6 +74,7 @@ class TB:
self.ptp_ts_sink = PtpTsSink(PtpTsBus.from_prefix(dut, "m_axis_ptp"), dut.clk, dut.rst)
dut.cfg_ifg.setimmediatevalue(0)
dut.cfg_tx_enable.setimmediatevalue(0)
async def reset(self):
self.dut.rst.setimmediatevalue(0)
@ -92,6 +93,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12):
tb = TB(dut)
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
await tb.reset()
@ -136,6 +138,7 @@ async def run_test_alignment(dut, payload_data=None, ifg=12):
byte_width = tb.source.width // 8
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
await tb.reset()

2
tb/axis_gmii_rx/test_axis_gmii_rx.py
View File

@ -59,6 +59,7 @@ class TB:
dut.clk_enable.setimmediatevalue(1)
dut.mii_select.setimmediatevalue(0)
dut.cfg_rx_enable.setimmediatevalue(0)
async def reset(self):
self.dut.rst.setimmediatevalue(0)
@ -96,6 +97,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12, enable_
tb.source.ifg = ifg
tb.dut.mii_select.value = mii_sel
tb.dut.cfg_rx_enable.value = 1
if enable_gen is not None:
tb.set_enable_generator(enable_gen())

2
tb/axis_gmii_tx/test_axis_gmii_tx.py
View File

@ -68,6 +68,7 @@ class TB:
dut.clk_enable.setimmediatevalue(1)
dut.mii_select.setimmediatevalue(0)
dut.cfg_ifg.setimmediatevalue(0)
dut.cfg_tx_enable.setimmediatevalue(0)
async def reset(self):
self.dut.rst.setimmediatevalue(0)
@ -104,6 +105,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12, enable_
tb = TB(dut)
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
tb.dut.mii_select.value = mii_sel
if enable_gen is not None:

3
tb/axis_xgmii_rx_32/test_axis_xgmii_rx_32.py
View File

@ -53,6 +53,8 @@ class TB:
self.ptp_clock = PtpClockSimTime(ts_64=dut.ptp_ts, clock=dut.clk)
dut.cfg_rx_enable.setimmediatevalue(0)
async def reset(self):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
@ -70,6 +72,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12):
tb = TB(dut)
tb.source.ifg = ifg
tb.dut.cfg_rx_enable.value = 1
await tb.reset()

3
tb/axis_xgmii_rx_64/test_axis_xgmii_rx_64.py
View File

@ -53,6 +53,8 @@ class TB:
self.ptp_clock = PtpClockSimTime(ts_64=dut.ptp_ts, clock=dut.clk)
dut.cfg_rx_enable.setimmediatevalue(0)
async def reset(self):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
@ -70,6 +72,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12):
tb = TB(dut)
tb.source.ifg = ifg
tb.dut.cfg_rx_enable.value = 1
await tb.reset()

3
tb/axis_xgmii_tx_32/test_axis_xgmii_tx_32.py
View File

@ -63,6 +63,7 @@ class TB:
self.ptp_ts_sink = PtpTsSink(PtpTsBus.from_prefix(dut, "m_axis_ptp"), dut.clk, dut.rst)
dut.cfg_ifg.setimmediatevalue(0)
dut.cfg_tx_enable.setimmediatevalue(0)
async def reset(self):
self.dut.rst.setimmediatevalue(0)
@ -81,6 +82,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12):
tb = TB(dut)
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
await tb.reset()
@ -121,6 +123,7 @@ async def run_test_alignment(dut, payload_data=None, ifg=12):
byte_width = tb.source.width // 8
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
await tb.reset()

3
tb/axis_xgmii_tx_64/test_axis_xgmii_tx_64.py
View File

@ -63,6 +63,7 @@ class TB:
self.ptp_ts_sink = PtpTsSink(PtpTsBus.from_prefix(dut, "m_axis_ptp"), dut.clk, dut.rst)
dut.cfg_ifg.setimmediatevalue(0)
dut.cfg_tx_enable.setimmediatevalue(0)
async def reset(self):
self.dut.rst.setimmediatevalue(0)
@ -81,6 +82,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12):
tb = TB(dut)
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
await tb.reset()
@ -125,6 +127,7 @@ async def run_test_alignment(dut, payload_data=None, ifg=12):
byte_width = tb.source.width // 8
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
await tb.reset()

9
tb/eth_mac_10g/test_eth_mac_10g.py
View File

@ -89,6 +89,8 @@ class TB:
dut.tx_pause_req.setimmediatevalue(0)
dut.cfg_ifg.setimmediatevalue(0)
dut.cfg_tx_enable.setimmediatevalue(0)
dut.cfg_rx_enable.setimmediatevalue(0)
dut.cfg_mcf_rx_eth_dst_mcast.setimmediatevalue(0)
dut.cfg_mcf_rx_check_eth_dst_mcast.setimmediatevalue(0)
dut.cfg_mcf_rx_eth_dst_ucast.setimmediatevalue(0)
@ -142,6 +144,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12):
tb.xgmii_source.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_rx_enable.value = 1
await tb.reset()
@ -186,6 +189,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12):
tb.xgmii_source.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
await tb.reset()
@ -231,6 +235,7 @@ async def run_test_tx_alignment(dut, payload_data=None, ifg=12):
tb.xgmii_source.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
await tb.reset()
@ -314,6 +319,8 @@ async def run_test_lfc(dut, ifg=12):
tb.xgmii_source.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
tb.dut.cfg_rx_enable.value = 1
await tb.reset()
@ -457,6 +464,8 @@ async def run_test_pfc(dut, ifg=12):
tb.xgmii_source.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
tb.dut.cfg_rx_enable.value = 1
await tb.reset()

5
tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py
View File

@ -76,6 +76,8 @@ class TB:
dut.ptp_ts_step.setimmediatevalue(0)
dut.cfg_ifg.setimmediatevalue(0)
dut.cfg_tx_enable.setimmediatevalue(0)
dut.cfg_rx_enable.setimmediatevalue(0)
async def reset(self):
self.dut.logic_rst.setimmediatevalue(0)
@ -101,6 +103,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12):
tb.xgmii_source.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_rx_enable.value = 1
await tb.reset()
@ -149,6 +152,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12):
tb.xgmii_source.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
await tb.reset()
@ -198,6 +202,7 @@ async def run_test_tx_alignment(dut, payload_data=None, ifg=12):
tb.xgmii_source.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
await tb.reset()

8
tb/eth_mac_1g/test_eth_mac_1g.py
View File

@ -96,6 +96,8 @@ class TB:
dut.tx_mii_select.setimmediatevalue(0)
dut.cfg_ifg.setimmediatevalue(0)
dut.cfg_tx_enable.setimmediatevalue(0)
dut.cfg_rx_enable.setimmediatevalue(0)
dut.cfg_mcf_rx_eth_dst_mcast.setimmediatevalue(0)
dut.cfg_mcf_rx_check_eth_dst_mcast.setimmediatevalue(0)
dut.cfg_mcf_rx_eth_dst_ucast.setimmediatevalue(0)
@ -185,6 +187,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, enab
tb.gmii_source.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_rx_enable.value = 1
tb.dut.rx_mii_select.value = mii_sel
tb.dut.tx_mii_select.value = mii_sel
@ -231,6 +234,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, enab
tb.gmii_source.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
tb.dut.rx_mii_select.value = mii_sel
tb.dut.tx_mii_select.value = mii_sel
@ -274,6 +278,8 @@ async def run_test_lfc(dut, ifg=12, enable_gen=None, mii_sel=True):
tb.gmii_source.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
tb.dut.cfg_rx_enable.value = 1
tb.dut.rx_mii_select.value = mii_sel
tb.dut.tx_mii_select.value = mii_sel
@ -423,6 +429,8 @@ async def run_test_pfc(dut, ifg=12, enable_gen=None, mii_sel=True):
tb.gmii_source.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
tb.dut.cfg_rx_enable.value = 1
tb.dut.rx_mii_select.value = mii_sel
tb.dut.tx_mii_select.value = mii_sel

4
tb/eth_mac_1g_fifo/test_eth_mac_1g_fifo.py
View File

@ -67,6 +67,8 @@ class TB:
dut.rx_mii_select.setimmediatevalue(0)
dut.tx_mii_select.setimmediatevalue(0)
dut.cfg_ifg.setimmediatevalue(0)
dut.cfg_tx_enable.setimmediatevalue(0)
dut.cfg_rx_enable.setimmediatevalue(0)
async def reset(self):
self.dut.logic_rst.setimmediatevalue(0)
@ -128,6 +130,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, enab
tb.gmii_source.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_rx_enable.value = 1
tb.dut.rx_mii_select.value = mii_sel
tb.dut.tx_mii_select.value = mii_sel
@ -161,6 +164,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, enab
tb.gmii_source.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
tb.dut.rx_mii_select.value = mii_sel
tb.dut.tx_mii_select.value = mii_sel

4
tb/eth_mac_1g_gmii/test_eth_mac_1g_gmii.py
View File

@ -54,6 +54,8 @@ class TB:
self.axis_sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "rx_axis"), dut.rx_clk, dut.rx_rst)
dut.cfg_ifg.setimmediatevalue(0)
dut.cfg_tx_enable.setimmediatevalue(0)
dut.cfg_rx_enable.setimmediatevalue(0)
async def reset(self):
self.dut.gtx_rst.setimmediatevalue(0)
@ -76,6 +78,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb.gmii_phy.rx.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_rx_enable.value = 1
tb.set_speed(speed)
@ -115,6 +118,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb.gmii_phy.rx.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
tb.set_speed(speed)

4
tb/eth_mac_1g_gmii_fifo/test_eth_mac_1g_gmii_fifo.py
View File

@ -55,6 +55,8 @@ class TB:
self.axis_sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "rx_axis"), dut.logic_clk, dut.logic_rst)
dut.cfg_ifg.setimmediatevalue(0)
dut.cfg_tx_enable.setimmediatevalue(0)
dut.cfg_rx_enable.setimmediatevalue(0)
async def reset(self):
self.dut.gtx_rst.setimmediatevalue(0)
@ -80,6 +82,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb.gmii_phy.rx.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_rx_enable.value = 1
tb.set_speed(speed)
@ -119,6 +122,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb.gmii_phy.rx.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
tb.set_speed(speed)

4
tb/eth_mac_1g_rgmii/test_eth_mac_1g_rgmii.py
View File

@ -51,6 +51,8 @@ class TB:
self.axis_sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "rx_axis"), dut.rx_clk, dut.rx_rst)
dut.cfg_ifg.setimmediatevalue(0)
dut.cfg_tx_enable.setimmediatevalue(0)
dut.cfg_rx_enable.setimmediatevalue(0)
dut.gtx_clk.setimmediatevalue(0)
dut.gtx_clk90.setimmediatevalue(0)
@ -87,6 +89,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb.rgmii_phy.rx.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_rx_enable.value = 1
await tb.reset()
@ -124,6 +127,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb.rgmii_phy.rx.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
await tb.reset()

4
tb/eth_mac_1g_rgmii_fifo/test_eth_mac_1g_rgmii_fifo.py
View File

@ -54,6 +54,8 @@ class TB:
self.axis_sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "rx_axis"), dut.logic_clk, dut.logic_rst)
dut.cfg_ifg.setimmediatevalue(0)
dut.cfg_tx_enable.setimmediatevalue(0)
dut.cfg_rx_enable.setimmediatevalue(0)
dut.gtx_clk.setimmediatevalue(0)
dut.gtx_clk90.setimmediatevalue(0)
@ -93,6 +95,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb.rgmii_phy.rx.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_rx_enable.value = 1
await tb.reset()
@ -130,6 +133,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb.rgmii_phy.rx.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
await tb.reset()

4
tb/eth_mac_mii/test_eth_mac_mii.py
View File

@ -51,6 +51,8 @@ class TB:
self.axis_sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "rx_axis"), dut.rx_clk, dut.rx_rst)
dut.cfg_ifg.setimmediatevalue(0)
dut.cfg_tx_enable.setimmediatevalue(0)
dut.cfg_rx_enable.setimmediatevalue(0)
async def reset(self):
self.dut.rst.setimmediatevalue(0)
@ -70,6 +72,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb.mii_phy.rx.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_rx_enable.value = 1
await tb.reset()
@ -97,6 +100,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb.mii_phy.rx.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
await tb.reset()

4
tb/eth_mac_mii_fifo/test_eth_mac_mii_fifo.py
View File

@ -54,6 +54,8 @@ class TB:
self.axis_sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "rx_axis"), dut.logic_clk, dut.logic_rst)
dut.cfg_ifg.setimmediatevalue(0)
dut.cfg_tx_enable.setimmediatevalue(0)
dut.cfg_rx_enable.setimmediatevalue(0)
async def reset(self):
self.dut.logic_rst.setimmediatevalue(0)
@ -73,6 +75,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb.mii_phy.rx.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_rx_enable.value = 1
await tb.reset()
@ -100,6 +103,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, spee
tb.mii_phy.rx.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
await tb.reset()

5
tb/eth_mac_phy_10g/test_eth_mac_phy_10g.py
View File

@ -84,6 +84,8 @@ class TB:
self.tx_ptp_ts_sink = PtpTsSink(PtpTsBus.from_prefix(dut, "tx_axis_ptp"), dut.tx_clk, dut.tx_rst)
dut.cfg_ifg.setimmediatevalue(0)
dut.cfg_tx_enable.setimmediatevalue(0)
dut.cfg_rx_enable.setimmediatevalue(0)
dut.cfg_tx_prbs31_enable.setimmediatevalue(0)
dut.cfg_rx_prbs31_enable.setimmediatevalue(0)
@ -108,6 +110,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12):
tb.serdes_source.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_rx_enable.value = 1
await tb.reset()
@ -161,6 +164,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12):
tb.serdes_source.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
await tb.reset()
@ -206,6 +210,7 @@ async def run_test_tx_alignment(dut, payload_data=None, ifg=12):
tb.serdes_source.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
await tb.reset()

5
tb/eth_mac_phy_10g_fifo/test_eth_mac_phy_10g_fifo.py
View File

@ -87,6 +87,8 @@ class TB:
dut.ptp_ts_step.setimmediatevalue(0)
dut.cfg_ifg.setimmediatevalue(0)
dut.cfg_tx_enable.setimmediatevalue(0)
dut.cfg_rx_enable.setimmediatevalue(0)
dut.cfg_tx_prbs31_enable.setimmediatevalue(0)
dut.cfg_rx_prbs31_enable.setimmediatevalue(0)
@ -114,6 +116,7 @@ async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12):
tb.serdes_source.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_rx_enable.value = 1
await tb.reset()
@ -169,6 +172,7 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12):
tb.serdes_source.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
await tb.reset()
@ -218,6 +222,7 @@ async def run_test_tx_alignment(dut, payload_data=None, ifg=12):
tb.serdes_source.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
await tb.reset()