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Convert generated frame joiner to verilog parametrized frame joiner

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Alex Forencich 2018-10-24 17:07:22 -07:00
parent fd7f65d5ad
commit fc6c07e5f9
5 changed files with 478 additions and 1074 deletions
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414
rtl/axis_frame_join.py
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#!/usr/bin/env python
"""
Generates an AXI Stream frame join module with a specific number of input ports
"""
from __future__ import print_function
import argparse
import math
from jinja2 import Template
def main():
parser = argparse.ArgumentParser(description=__doc__.strip())
parser.add_argument('-p', '--ports', type=int, default=4, help="number of ports")
parser.add_argument('-n', '--name', type=str, help="module name")
parser.add_argument('-o', '--output', type=str, help="output file name")
args = parser.parse_args()
try:
generate(**args.__dict__)
except IOError as ex:
print(ex)
exit(1)
def generate(ports=4, name=None, output=None):
if name is None:
name = "axis_frame_join_{0}".format(ports)
if output is None:
output = name + ".v"
print("Opening file '{0}'...".format(output))
output_file = open(output, 'w')
print("Generating {0} port AXI Stream frame joiner {1}...".format(ports, name))
select_width = int(math.ceil(math.log(ports, 2)))
t = Template(u"""/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream {{n}} port frame joiner
*/
module {{name}} #
(
parameter TAG_ENABLE = 1,
parameter TAG_WIDTH = 16
)
(
input wire clk,
input wire rst,
/*
* AXI inputs
*/
{%- for p in ports %}
input wire [7:0] input_{{p}}_axis_tdata,
input wire input_{{p}}_axis_tvalid,
output wire input_{{p}}_axis_tready,
input wire input_{{p}}_axis_tlast,
input wire input_{{p}}_axis_tuser,
{% endfor %}
/*
* AXI output
*/
output wire [7:0] output_axis_tdata,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
output wire output_axis_tuser,
/*
* Configuration
*/
input wire [TAG_WIDTH-1:0] tag,
/*
* Status signals
*/
output wire busy
);
localparam TAG_BYTE_WIDTH = (TAG_WIDTH + 7) / 8;
// state register
localparam [1:0]
STATE_IDLE = 2'd0,
STATE_WRITE_TAG = 2'd1,
STATE_TRANSFER = 2'd2;
reg [1:0] state_reg = STATE_IDLE, state_next;
reg [2:0] frame_ptr_reg = 3'd0, frame_ptr_next;
reg [{{w-1}}:0] port_sel_reg = {{w}}'d0, port_sel_next;
reg busy_reg = 1'b0, busy_next;
reg [7:0] input_tdata;
reg input_tvalid;
reg input_tlast;
reg input_tuser;
reg output_tuser_reg = 1'b0, output_tuser_next;
{% for p in ports %}
reg input_{{p}}_axis_tready_reg = 1'b0, input_{{p}}_axis_tready_next;
{%- endfor %}
// internal datapath
reg [7:0] output_axis_tdata_int;
reg output_axis_tvalid_int;
reg output_axis_tready_int_reg = 1'b0;
reg output_axis_tlast_int;
reg output_axis_tuser_int;
wire output_axis_tready_int_early;
{% for p in ports %}
assign input_{{p}}_axis_tready = input_{{p}}_axis_tready_reg;
{%- endfor %}
assign busy = busy_reg;
always @* begin
// input port mux
case (port_sel_reg)
{%- for p in ports %}
{{w}}'d{{p}}: begin
input_tdata = input_{{p}}_axis_tdata;
input_tvalid = input_{{p}}_axis_tvalid;
input_tlast = input_{{p}}_axis_tlast;
input_tuser = input_{{p}}_axis_tuser;
end
{%- endfor %}
endcase
end
integer offset, i;
always @* begin
state_next = STATE_IDLE;
frame_ptr_next = frame_ptr_reg;
port_sel_next = port_sel_reg;
{% for p in ports %}
input_{{p}}_axis_tready_next = 1'b0;
{%- endfor %}
output_axis_tdata_int = 8'd0;
output_axis_tvalid_int = 1'b0;
output_axis_tlast_int = 1'b0;
output_axis_tuser_int = 1'b0;
output_tuser_next = output_tuser_reg;
case (state_reg)
STATE_IDLE: begin
// idle state - wait for data
frame_ptr_next = 3'd0;
port_sel_next = {{w}}'d0;
output_tuser_next = 1'b0;
if (TAG_ENABLE) begin
// next cycle if started will send tag, so do not enable input
input_0_axis_tready_next = 1'b0;
end else begin
// next cycle if started will send data, so enable input
input_0_axis_tready_next = output_axis_tready_int_early;
end
if (input_0_axis_tvalid) begin
// input 0 valid; start transferring data
if (TAG_ENABLE) begin
// tag enabled, so transmit it
if (output_axis_tready_int_reg) begin
// output is ready, so short-circuit first tag byte
frame_ptr_next = 3'd1;
output_axis_tdata_int = tag[(TAG_BYTE_WIDTH-1)*8 +: 8];
output_axis_tvalid_int = 1'b1;
end
state_next = STATE_WRITE_TAG;
end else begin
// tag disabled, so transmit data
if (output_axis_tready_int_reg) begin
// output is ready, so short-circuit first data byte
output_axis_tdata_int = input_0_axis_tdata;
output_axis_tvalid_int = 1'b1;
end
state_next = STATE_TRANSFER;
end
end else begin
state_next = STATE_IDLE;
end
end
STATE_WRITE_TAG: begin
// write tag data
if (output_axis_tready_int_reg) begin
// output ready, so send tag byte
state_next = STATE_WRITE_TAG;
frame_ptr_next = frame_ptr_reg + 1;
output_axis_tvalid_int = 1'b1;
offset = 0;
if (TAG_ENABLE) begin
for (i = TAG_BYTE_WIDTH-1; i >= 0; i = i - 1) begin
if (frame_ptr_reg == offset) begin
output_axis_tdata_int = tag[i*8 +: 8];
end
offset = offset + 1;
end
end
if (frame_ptr_reg == offset-1) begin
input_0_axis_tready_next = output_axis_tready_int_early;
state_next = STATE_TRANSFER;
end
end else begin
state_next = STATE_WRITE_TAG;
end
end
STATE_TRANSFER: begin
// transfer input data
// set ready for current input
case (port_sel_reg)
{%- for p in ports %}
{{w}}'d{{p}}: input_{{p}}_axis_tready_next = output_axis_tready_int_early;
{%- endfor %}
endcase
if (input_tvalid & output_axis_tready_int_reg) begin
// output ready, transfer byte
state_next = STATE_TRANSFER;
output_axis_tdata_int = input_tdata;
output_axis_tvalid_int = input_tvalid;
if (input_tlast) begin
// last flag received, switch to next port
port_sel_next = port_sel_reg + 1;
// save tuser - assert tuser out if ANY tuser asserts received
output_tuser_next = output_tuser_next | input_tuser;
// disable input
{%- for p in ports %}
input_{{p}}_axis_tready_next = 1'b0;
{%- endfor %}
if (port_sel_reg == {{w}}'d{{n-1}}) begin
// last port - send tlast and tuser and revert to idle
output_axis_tlast_int = 1'b1;
output_axis_tuser_int = output_tuser_next;
state_next = STATE_IDLE;
end else begin
// otherwise, disable enable next port
case (port_sel_next)
{%- for p in ports %}
{{w}}'d{{p}}: input_{{p}}_axis_tready_next = output_axis_tready_int_early;
{%- endfor %}
endcase
end
end
end else begin
state_next = STATE_TRANSFER;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
frame_ptr_reg <= 3'd0;
port_sel_reg <= {{w}}'d0;
{%- for p in ports %}
input_{{p}}_axis_tready_reg <= 1'b0;
{%- endfor %}
output_tuser_reg <= 1'b0;
busy_reg <= 1'b0;
end else begin
state_reg <= state_next;
frame_ptr_reg <= frame_ptr_next;
port_sel_reg <= port_sel_next;
{% for p in ports %}
input_{{p}}_axis_tready_reg <= input_{{p}}_axis_tready_next;
{%- endfor %}
output_tuser_reg <= output_tuser_next;
busy_reg <= state_next != STATE_IDLE;
end
end
// output datapath logic
reg [7:0] output_axis_tdata_reg = 8'd0;
reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next;
reg output_axis_tlast_reg = 1'b0;
reg output_axis_tuser_reg = 1'b0;
reg [7:0] temp_axis_tdata_reg = 8'd0;
reg temp_axis_tvalid_reg = 1'b0, temp_axis_tvalid_next;
reg temp_axis_tlast_reg = 1'b0;
reg temp_axis_tuser_reg = 1'b0;
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_axis_temp_to_output;
assign output_axis_tdata = output_axis_tdata_reg;
assign output_axis_tvalid = output_axis_tvalid_reg;
assign output_axis_tlast = output_axis_tlast_reg;
assign output_axis_tuser = output_axis_tuser_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign output_axis_tready_int_early = output_axis_tready | (~temp_axis_tvalid_reg & (~output_axis_tvalid_reg | ~output_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
output_axis_tvalid_next = output_axis_tvalid_reg;
temp_axis_tvalid_next = temp_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (output_axis_tready_int_reg) begin
// input is ready
if (output_axis_tready | ~output_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
output_axis_tvalid_next = output_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_axis_tvalid_next = output_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (output_axis_tready) begin
// input is not ready, but output is ready
output_axis_tvalid_next = temp_axis_tvalid_reg;
temp_axis_tvalid_next = 1'b0;
store_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
output_axis_tvalid_reg <= 1'b0;
output_axis_tready_int_reg <= 1'b0;
temp_axis_tvalid_reg <= 1'b0;
end else begin
output_axis_tvalid_reg <= output_axis_tvalid_next;
output_axis_tready_int_reg <= output_axis_tready_int_early;
temp_axis_tvalid_reg <= temp_axis_tvalid_next;
end
// datapath
if (store_axis_int_to_output) begin
output_axis_tdata_reg <= output_axis_tdata_int;
output_axis_tlast_reg <= output_axis_tlast_int;
output_axis_tuser_reg <= output_axis_tuser_int;
end else if (store_axis_temp_to_output) begin
output_axis_tdata_reg <= temp_axis_tdata_reg;
output_axis_tlast_reg <= temp_axis_tlast_reg;
output_axis_tuser_reg <= temp_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_axis_tdata_reg <= output_axis_tdata_int;
temp_axis_tlast_reg <= output_axis_tlast_int;
temp_axis_tuser_reg <= output_axis_tuser_int;
end
end
endmodule
""")
output_file.write(t.render(
n=ports,
w=select_width,
name=name,
ports=range(ports)
))
print("Done")
if __name__ == "__main__":
main()

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rtl/axis_frame_join.v Normal file
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/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream frame joiner
*/
module axis_frame_join #
(
parameter DATA_WIDTH = 8,
parameter S_COUNT = 4,
parameter TAG_ENABLE = 1,
parameter TAG_WIDTH = 16
)
(
input wire clk,
input wire rst,
/*
* AXI inputs
*/
input wire [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata,
input wire [S_COUNT-1:0] s_axis_tvalid,
output wire [S_COUNT-1:0] s_axis_tready,
input wire [S_COUNT-1:0] s_axis_tlast,
input wire [S_COUNT-1:0] s_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire m_axis_tuser,
/*
* Configuration
*/
input wire [TAG_WIDTH-1:0] tag,
/*
* Status signals
*/
output wire busy
);
parameter CL_S_COUNT = $clog2(S_COUNT);
parameter TAG_WORD_WIDTH = (TAG_WIDTH + DATA_WIDTH - 1) / DATA_WIDTH;
parameter CL_TAG_WORD_WIDTH = $clog2(TAG_WORD_WIDTH);
// state register
localparam [1:0]
STATE_IDLE = 2'd0,
STATE_WRITE_TAG = 2'd1,
STATE_TRANSFER = 2'd2;
reg [1:0] state_reg = STATE_IDLE, state_next;
reg [CL_TAG_WORD_WIDTH-1:0] frame_ptr_reg = {CL_TAG_WORD_WIDTH{1'b0}}, frame_ptr_next;
reg [CL_S_COUNT-1:0] port_sel_reg = {CL_S_COUNT{1'b0}}, port_sel_next;
reg busy_reg = 1'b0, busy_next;
reg output_tuser_reg = 1'b0, output_tuser_next;
reg [S_COUNT-1:0] s_axis_tready_reg = {S_COUNT{1'b0}}, s_axis_tready_next;
// internal datapath
reg [DATA_WIDTH-1:0] m_axis_tdata_int;
reg m_axis_tvalid_int;
reg m_axis_tready_int_reg = 1'b0;
reg m_axis_tlast_int;
reg m_axis_tuser_int;
wire m_axis_tready_int_early;
assign s_axis_tready = s_axis_tready_reg;
assign busy = busy_reg;
wire [DATA_WIDTH-1:0] input_tdata = s_axis_tdata[port_sel_reg*DATA_WIDTH +: DATA_WIDTH];
wire input_tvalid = s_axis_tvalid[port_sel_reg];
wire input_tlast = s_axis_tlast[port_sel_reg];
wire input_tuser = s_axis_tuser[port_sel_reg];
always @* begin
state_next = STATE_IDLE;
frame_ptr_next = frame_ptr_reg;
port_sel_next = port_sel_reg;
s_axis_tready_next = {S_COUNT{1'b0}};
m_axis_tdata_int = 8'd0;
m_axis_tvalid_int = 1'b0;
m_axis_tlast_int = 1'b0;
m_axis_tuser_int = 1'b0;
output_tuser_next = output_tuser_reg;
case (state_reg)
STATE_IDLE: begin
// idle state - wait for data
frame_ptr_next = {CL_TAG_WORD_WIDTH{1'b0}};
port_sel_next = {CL_S_COUNT{1'b0}};
output_tuser_next = 1'b0;
if (TAG_ENABLE) begin
// next cycle if started will send tag, so do not enable input
s_axis_tready_next = 1'b0;
end else begin
// next cycle if started will send data, so enable input
s_axis_tready_next = m_axis_tready_int_early;
end
if (s_axis_tvalid) begin
// input 0 valid; start transferring data
if (TAG_ENABLE) begin
// tag enabled, so transmit it
if (m_axis_tready_int_reg) begin
// output is ready, so short-circuit first tag word
frame_ptr_next = 1;
m_axis_tdata_int = tag;
m_axis_tvalid_int = 1'b1;
end
state_next = STATE_WRITE_TAG;
end else begin
// tag disabled, so transmit data
if (m_axis_tready_int_reg) begin
// output is ready, so short-circuit first data word
m_axis_tdata_int = s_axis_tdata;
m_axis_tvalid_int = 1'b1;
end
state_next = STATE_TRANSFER;
end
end else begin
state_next = STATE_IDLE;
end
end
STATE_WRITE_TAG: begin
// write tag data
if (m_axis_tready_int_reg) begin
// output ready, so send tag word
state_next = STATE_WRITE_TAG;
frame_ptr_next = frame_ptr_reg + 1;
m_axis_tvalid_int = 1'b1;
m_axis_tdata_int = tag >> frame_ptr_reg*DATA_WIDTH;
if (frame_ptr_reg == TAG_WORD_WIDTH-1) begin
s_axis_tready_next = m_axis_tready_int_early << 0;
state_next = STATE_TRANSFER;
end
end else begin
state_next = STATE_WRITE_TAG;
end
end
STATE_TRANSFER: begin
// transfer input data
// set ready for current input
s_axis_tready_next = m_axis_tready_int_early << port_sel_reg;
if (input_tvalid && m_axis_tready_int_reg) begin
// output ready, transfer byte
state_next = STATE_TRANSFER;
m_axis_tdata_int = input_tdata;
m_axis_tvalid_int = input_tvalid;
if (input_tlast) begin
// last flag received, switch to next port
port_sel_next = port_sel_reg + 1;
// save tuser - assert tuser out if ANY tuser asserts received
output_tuser_next = output_tuser_next | input_tuser;
// disable input
s_axis_tready_next = {S_COUNT{1'b0}};
if (S_COUNT == 1 || port_sel_reg == S_COUNT-1) begin
// last port - send tlast and tuser and revert to idle
m_axis_tlast_int = 1'b1;
m_axis_tuser_int = output_tuser_next;
state_next = STATE_IDLE;
end else begin
// otherwise, disable enable next port
s_axis_tready_next = m_axis_tready_int_early << port_sel_next;
end
end
end else begin
state_next = STATE_TRANSFER;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
frame_ptr_reg <= {CL_TAG_WORD_WIDTH{1'b0}};
port_sel_reg <= {CL_S_COUNT{1'b0}};
s_axis_tready_reg <= {S_COUNT{1'b0}};
output_tuser_reg <= 1'b0;
busy_reg <= 1'b0;
end else begin
state_reg <= state_next;
frame_ptr_reg <= frame_ptr_next;
port_sel_reg <= port_sel_next;
s_axis_tready_reg <= s_axis_tready_next;
output_tuser_reg <= output_tuser_next;
busy_reg <= state_next != STATE_IDLE;
end
end
// output datapath logic
reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
reg m_axis_tlast_reg = 1'b0;
reg m_axis_tuser_reg = 1'b0;
reg [DATA_WIDTH-1:0] temp_m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
reg temp_m_axis_tlast_reg = 1'b0;
reg temp_m_axis_tuser_reg = 1'b0;
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_axis_temp_to_output;
assign m_axis_tdata = m_axis_tdata_reg;
assign m_axis_tvalid = m_axis_tvalid_reg;
assign m_axis_tlast = m_axis_tlast_reg;
assign m_axis_tuser = m_axis_tuser_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
m_axis_tvalid_next = m_axis_tvalid_reg;
temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (m_axis_tready_int_reg) begin
// input is ready
if (m_axis_tready || !m_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (m_axis_tready) begin
// input is not ready, but output is ready
m_axis_tvalid_next = temp_m_axis_tvalid_reg;
temp_m_axis_tvalid_next = 1'b0;
store_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
m_axis_tvalid_reg <= 1'b0;
m_axis_tready_int_reg <= 1'b0;
temp_m_axis_tvalid_reg <= 1'b0;
end else begin
m_axis_tvalid_reg <= m_axis_tvalid_next;
m_axis_tready_int_reg <= m_axis_tready_int_early;
temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
end
// datapath
if (store_axis_int_to_output) begin
m_axis_tdata_reg <= m_axis_tdata_int;
m_axis_tlast_reg <= m_axis_tlast_int;
m_axis_tuser_reg <= m_axis_tuser_int;
end else if (store_axis_temp_to_output) begin
m_axis_tdata_reg <= temp_m_axis_tdata_reg;
m_axis_tlast_reg <= temp_m_axis_tlast_reg;
m_axis_tuser_reg <= temp_m_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_m_axis_tdata_reg <= m_axis_tdata_int;
temp_m_axis_tlast_reg <= m_axis_tlast_int;
temp_m_axis_tuser_reg <= m_axis_tuser_int;
end
end
endmodule

404
rtl/axis_frame_join_4.v
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@ -1,404 +0,0 @@
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream 4 port frame joiner
*/
module axis_frame_join_4 #
(
parameter TAG_ENABLE = 1,
parameter TAG_WIDTH = 16
)
(
input wire clk,
input wire rst,
/*
* AXI inputs
*/
input wire [7:0] input_0_axis_tdata,
input wire input_0_axis_tvalid,
output wire input_0_axis_tready,
input wire input_0_axis_tlast,
input wire input_0_axis_tuser,
input wire [7:0] input_1_axis_tdata,
input wire input_1_axis_tvalid,
output wire input_1_axis_tready,
input wire input_1_axis_tlast,
input wire input_1_axis_tuser,
input wire [7:0] input_2_axis_tdata,
input wire input_2_axis_tvalid,
output wire input_2_axis_tready,
input wire input_2_axis_tlast,
input wire input_2_axis_tuser,
input wire [7:0] input_3_axis_tdata,
input wire input_3_axis_tvalid,
output wire input_3_axis_tready,
input wire input_3_axis_tlast,
input wire input_3_axis_tuser,
/*
* AXI output
*/
output wire [7:0] output_axis_tdata,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
output wire output_axis_tuser,
/*
* Configuration
*/
input wire [TAG_WIDTH-1:0] tag,
/*
* Status signals
*/
output wire busy
);
localparam TAG_BYTE_WIDTH = (TAG_WIDTH + 7) / 8;
// state register
localparam [1:0]
STATE_IDLE = 2'd0,
STATE_WRITE_TAG = 2'd1,
STATE_TRANSFER = 2'd2;
reg [1:0] state_reg = STATE_IDLE, state_next;
reg [2:0] frame_ptr_reg = 3'd0, frame_ptr_next;
reg [1:0] port_sel_reg = 2'd0, port_sel_next;
reg busy_reg = 1'b0, busy_next;
reg [7:0] input_tdata;
reg input_tvalid;
reg input_tlast;
reg input_tuser;
reg output_tuser_reg = 1'b0, output_tuser_next;
reg input_0_axis_tready_reg = 1'b0, input_0_axis_tready_next;
reg input_1_axis_tready_reg = 1'b0, input_1_axis_tready_next;
reg input_2_axis_tready_reg = 1'b0, input_2_axis_tready_next;
reg input_3_axis_tready_reg = 1'b0, input_3_axis_tready_next;
// internal datapath
reg [7:0] output_axis_tdata_int;
reg output_axis_tvalid_int;
reg output_axis_tready_int_reg = 1'b0;
reg output_axis_tlast_int;
reg output_axis_tuser_int;
wire output_axis_tready_int_early;
assign input_0_axis_tready = input_0_axis_tready_reg;
assign input_1_axis_tready = input_1_axis_tready_reg;
assign input_2_axis_tready = input_2_axis_tready_reg;
assign input_3_axis_tready = input_3_axis_tready_reg;
assign busy = busy_reg;
always @* begin
// input port mux
case (port_sel_reg)
2'd0: begin
input_tdata = input_0_axis_tdata;
input_tvalid = input_0_axis_tvalid;
input_tlast = input_0_axis_tlast;
input_tuser = input_0_axis_tuser;
end
2'd1: begin
input_tdata = input_1_axis_tdata;
input_tvalid = input_1_axis_tvalid;
input_tlast = input_1_axis_tlast;
input_tuser = input_1_axis_tuser;
end
2'd2: begin
input_tdata = input_2_axis_tdata;
input_tvalid = input_2_axis_tvalid;
input_tlast = input_2_axis_tlast;
input_tuser = input_2_axis_tuser;
end
2'd3: begin
input_tdata = input_3_axis_tdata;
input_tvalid = input_3_axis_tvalid;
input_tlast = input_3_axis_tlast;
input_tuser = input_3_axis_tuser;
end
endcase
end
integer offset, i;
always @* begin
state_next = STATE_IDLE;
frame_ptr_next = frame_ptr_reg;
port_sel_next = port_sel_reg;
input_0_axis_tready_next = 1'b0;
input_1_axis_tready_next = 1'b0;
input_2_axis_tready_next = 1'b0;
input_3_axis_tready_next = 1'b0;
output_axis_tdata_int = 8'd0;
output_axis_tvalid_int = 1'b0;
output_axis_tlast_int = 1'b0;
output_axis_tuser_int = 1'b0;
output_tuser_next = output_tuser_reg;
case (state_reg)
STATE_IDLE: begin
// idle state - wait for data
frame_ptr_next = 3'd0;
port_sel_next = 2'd0;
output_tuser_next = 1'b0;
if (TAG_ENABLE) begin
// next cycle if started will send tag, so do not enable input
input_0_axis_tready_next = 1'b0;
end else begin
// next cycle if started will send data, so enable input
input_0_axis_tready_next = output_axis_tready_int_early;
end
if (input_0_axis_tvalid) begin
// input 0 valid; start transferring data
if (TAG_ENABLE) begin
// tag enabled, so transmit it
if (output_axis_tready_int_reg) begin
// output is ready, so short-circuit first tag byte
frame_ptr_next = 3'd1;
output_axis_tdata_int = tag[(TAG_BYTE_WIDTH-1)*8 +: 8];
output_axis_tvalid_int = 1'b1;
end
state_next = STATE_WRITE_TAG;
end else begin
// tag disabled, so transmit data
if (output_axis_tready_int_reg) begin
// output is ready, so short-circuit first data byte
output_axis_tdata_int = input_0_axis_tdata;
output_axis_tvalid_int = 1'b1;
end
state_next = STATE_TRANSFER;
end
end else begin
state_next = STATE_IDLE;
end
end
STATE_WRITE_TAG: begin
// write tag data
if (output_axis_tready_int_reg) begin
// output ready, so send tag byte
state_next = STATE_WRITE_TAG;
frame_ptr_next = frame_ptr_reg + 1;
output_axis_tvalid_int = 1'b1;
offset = 0;
if (TAG_ENABLE) begin
for (i = TAG_BYTE_WIDTH-1; i >= 0; i = i - 1) begin
if (frame_ptr_reg == offset) begin
output_axis_tdata_int = tag[i*8 +: 8];
end
offset = offset + 1;
end
end
if (frame_ptr_reg == offset-1) begin
input_0_axis_tready_next = output_axis_tready_int_early;
state_next = STATE_TRANSFER;
end
end else begin
state_next = STATE_WRITE_TAG;
end
end
STATE_TRANSFER: begin
// transfer input data
// set ready for current input
case (port_sel_reg)
2'd0: input_0_axis_tready_next = output_axis_tready_int_early;
2'd1: input_1_axis_tready_next = output_axis_tready_int_early;
2'd2: input_2_axis_tready_next = output_axis_tready_int_early;
2'd3: input_3_axis_tready_next = output_axis_tready_int_early;
endcase
if (input_tvalid & output_axis_tready_int_reg) begin
// output ready, transfer byte
state_next = STATE_TRANSFER;
output_axis_tdata_int = input_tdata;
output_axis_tvalid_int = input_tvalid;
if (input_tlast) begin
// last flag received, switch to next port
port_sel_next = port_sel_reg + 1;
// save tuser - assert tuser out if ANY tuser asserts received
output_tuser_next = output_tuser_next | input_tuser;
// disable input
input_0_axis_tready_next = 1'b0;
input_1_axis_tready_next = 1'b0;
input_2_axis_tready_next = 1'b0;
input_3_axis_tready_next = 1'b0;
if (port_sel_reg == 2'd3) begin
// last port - send tlast and tuser and revert to idle
output_axis_tlast_int = 1'b1;
output_axis_tuser_int = output_tuser_next;
state_next = STATE_IDLE;
end else begin
// otherwise, disable enable next port
case (port_sel_next)
2'd0: input_0_axis_tready_next = output_axis_tready_int_early;
2'd1: input_1_axis_tready_next = output_axis_tready_int_early;
2'd2: input_2_axis_tready_next = output_axis_tready_int_early;
2'd3: input_3_axis_tready_next = output_axis_tready_int_early;
endcase
end
end
end else begin
state_next = STATE_TRANSFER;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
frame_ptr_reg <= 3'd0;
port_sel_reg <= 2'd0;
input_0_axis_tready_reg <= 1'b0;
input_1_axis_tready_reg <= 1'b0;
input_2_axis_tready_reg <= 1'b0;
input_3_axis_tready_reg <= 1'b0;
output_tuser_reg <= 1'b0;
busy_reg <= 1'b0;
end else begin
state_reg <= state_next;
frame_ptr_reg <= frame_ptr_next;
port_sel_reg <= port_sel_next;
input_0_axis_tready_reg <= input_0_axis_tready_next;
input_1_axis_tready_reg <= input_1_axis_tready_next;
input_2_axis_tready_reg <= input_2_axis_tready_next;
input_3_axis_tready_reg <= input_3_axis_tready_next;
output_tuser_reg <= output_tuser_next;
busy_reg <= state_next != STATE_IDLE;
end
end
// output datapath logic
reg [7:0] output_axis_tdata_reg = 8'd0;
reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next;
reg output_axis_tlast_reg = 1'b0;
reg output_axis_tuser_reg = 1'b0;
reg [7:0] temp_axis_tdata_reg = 8'd0;
reg temp_axis_tvalid_reg = 1'b0, temp_axis_tvalid_next;
reg temp_axis_tlast_reg = 1'b0;
reg temp_axis_tuser_reg = 1'b0;
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_axis_temp_to_output;
assign output_axis_tdata = output_axis_tdata_reg;
assign output_axis_tvalid = output_axis_tvalid_reg;
assign output_axis_tlast = output_axis_tlast_reg;
assign output_axis_tuser = output_axis_tuser_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign output_axis_tready_int_early = output_axis_tready | (~temp_axis_tvalid_reg & (~output_axis_tvalid_reg | ~output_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
output_axis_tvalid_next = output_axis_tvalid_reg;
temp_axis_tvalid_next = temp_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (output_axis_tready_int_reg) begin
// input is ready
if (output_axis_tready | ~output_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
output_axis_tvalid_next = output_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_axis_tvalid_next = output_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (output_axis_tready) begin
// input is not ready, but output is ready
output_axis_tvalid_next = temp_axis_tvalid_reg;
temp_axis_tvalid_next = 1'b0;
store_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
output_axis_tvalid_reg <= 1'b0;
output_axis_tready_int_reg <= 1'b0;
temp_axis_tvalid_reg <= 1'b0;
end else begin
output_axis_tvalid_reg <= output_axis_tvalid_next;
output_axis_tready_int_reg <= output_axis_tready_int_early;
temp_axis_tvalid_reg <= temp_axis_tvalid_next;
end
// datapath
if (store_axis_int_to_output) begin
output_axis_tdata_reg <= output_axis_tdata_int;
output_axis_tlast_reg <= output_axis_tlast_int;
output_axis_tuser_reg <= output_axis_tuser_int;
end else if (store_axis_temp_to_output) begin
output_axis_tdata_reg <= temp_axis_tdata_reg;
output_axis_tlast_reg <= temp_axis_tlast_reg;
output_axis_tuser_reg <= temp_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_axis_tdata_reg <= output_axis_tdata_int;
temp_axis_tlast_reg <= output_axis_tlast_int;
temp_axis_tuser_reg <= output_axis_tuser_int;
end
end
endmodule

298
tb/test_axis_frame_join_4.py
View File

@ -29,8 +29,8 @@ import struct
import axis_ep
module = 'axis_frame_join_4'
testbench = 'test_%s' % module
module = 'axis_frame_join'
testbench = 'test_%s_4' % module
srcs = []
@ -44,6 +44,8 @@ build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
DATA_WIDTH = 8
S_COUNT = 4
TAG_ENABLE = 1
TAG_WIDTH = 16
@ -52,109 +54,65 @@ def bench():
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_0_axis_tdata = Signal(intbv(0)[8:])
input_0_axis_tvalid = Signal(bool(0))
input_0_axis_tlast = Signal(bool(0))
input_0_axis_tuser = Signal(bool(0))
input_1_axis_tdata = Signal(intbv(0)[8:])
input_1_axis_tvalid = Signal(bool(0))
input_1_axis_tlast = Signal(bool(0))
input_1_axis_tuser = Signal(bool(0))
input_2_axis_tdata = Signal(intbv(0)[8:])
input_2_axis_tvalid = Signal(bool(0))
input_2_axis_tlast = Signal(bool(0))
input_2_axis_tuser = Signal(bool(0))
input_3_axis_tdata = Signal(intbv(0)[8:])
input_3_axis_tvalid = Signal(bool(0))
input_3_axis_tlast = Signal(bool(0))
input_3_axis_tuser = Signal(bool(0))
output_axis_tready = Signal(bool(0))
s_axis_tdata_list = [Signal(intbv(0)[DATA_WIDTH:]) for i in range(S_COUNT)]
s_axis_tvalid_list = [Signal(bool(0)) for i in range(S_COUNT)]
s_axis_tlast_list = [Signal(bool(0)) for i in range(S_COUNT)]
s_axis_tuser_list = [Signal(bool(0)) for i in range(S_COUNT)]
s_axis_tdata = ConcatSignal(*reversed(s_axis_tdata_list))
s_axis_tvalid = ConcatSignal(*reversed(s_axis_tvalid_list))
s_axis_tlast = ConcatSignal(*reversed(s_axis_tlast_list))
s_axis_tuser = ConcatSignal(*reversed(s_axis_tuser_list))
m_axis_tready = Signal(bool(0))
tag = Signal(intbv(0)[TAG_WIDTH:])
# Outputs
input_0_axis_tready = Signal(bool(0))
input_1_axis_tready = Signal(bool(0))
input_2_axis_tready = Signal(bool(0))
input_3_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[8:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0))
s_axis_tready = Signal(intbv(0)[S_COUNT:])
s_axis_tready_list = [s_axis_tready(i) for i in range(S_COUNT)]
m_axis_tdata = Signal(intbv(0)[8:])
m_axis_tvalid = Signal(bool(0))
m_axis_tlast = Signal(bool(0))
m_axis_tuser = Signal(bool(0))
busy = Signal(bool(0))
# sources and sinks
source_0_pause = Signal(bool(0))
source_1_pause = Signal(bool(0))
source_2_pause = Signal(bool(0))
source_3_pause = Signal(bool(0))
source_pause_list = []
source_list = []
source_logic_list = []
sink_pause = Signal(bool(0))
source_0 = axis_ep.AXIStreamSource()
for k in range(S_COUNT):
s = axis_ep.AXIStreamSource()
p = Signal(bool(0))
source_0_logic = source_0.create_logic(
clk,
rst,
tdata=input_0_axis_tdata,
tvalid=input_0_axis_tvalid,
tready=input_0_axis_tready,
tlast=input_0_axis_tlast,
tuser=input_0_axis_tuser,
pause=source_0_pause,
name='source_0'
)
source_list.append(s)
source_pause_list.append(p)
source_1 = axis_ep.AXIStreamSource()
source_1_logic = source_1.create_logic(
clk,
rst,
tdata=input_1_axis_tdata,
tvalid=input_1_axis_tvalid,
tready=input_1_axis_tready,
tlast=input_1_axis_tlast,
tuser=input_1_axis_tuser,
pause=source_1_pause,
name='source_1'
)
source_2 = axis_ep.AXIStreamSource()
source_2_logic = source_2.create_logic(
clk,
rst,
tdata=input_2_axis_tdata,
tvalid=input_2_axis_tvalid,
tready=input_2_axis_tready,
tlast=input_2_axis_tlast,
tuser=input_2_axis_tuser,
pause=source_2_pause,
name='source_2'
)
source_3 = axis_ep.AXIStreamSource()
source_3_logic = source_3.create_logic(
clk,
rst,
tdata=input_3_axis_tdata,
tvalid=input_3_axis_tvalid,
tready=input_3_axis_tready,
tlast=input_3_axis_tlast,
tuser=input_3_axis_tuser,
pause=source_3_pause,
name='source_3'
)
source_logic_list.append(s.create_logic(
clk,
rst,
tdata=s_axis_tdata_list[k],
tvalid=s_axis_tvalid_list[k],
tready=s_axis_tready_list[k],
tlast=s_axis_tlast_list[k],
tuser=s_axis_tuser_list[k],
pause=p,
name='source_%d' % k
))
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(
clk,
rst,
tdata=output_axis_tdata,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
tdata=m_axis_tdata,
tvalid=m_axis_tvalid,
tready=m_axis_tready,
tlast=m_axis_tlast,
tuser=m_axis_tuser,
pause=sink_pause,
name='sink'
)
@ -169,35 +127,17 @@ def bench():
rst=rst,
current_test=current_test,
input_0_axis_tdata=input_0_axis_tdata,
input_0_axis_tvalid=input_0_axis_tvalid,
input_0_axis_tready=input_0_axis_tready,
input_0_axis_tlast=input_0_axis_tlast,
input_0_axis_tuser=input_0_axis_tuser,
s_axis_tdata=s_axis_tdata,
s_axis_tvalid=s_axis_tvalid,
s_axis_tready=s_axis_tready,
s_axis_tlast=s_axis_tlast,
s_axis_tuser=s_axis_tuser,
input_1_axis_tdata=input_1_axis_tdata,
input_1_axis_tvalid=input_1_axis_tvalid,
input_1_axis_tready=input_1_axis_tready,
input_1_axis_tlast=input_1_axis_tlast,
input_1_axis_tuser=input_1_axis_tuser,
input_2_axis_tdata=input_2_axis_tdata,
input_2_axis_tvalid=input_2_axis_tvalid,
input_2_axis_tready=input_2_axis_tready,
input_2_axis_tlast=input_2_axis_tlast,
input_2_axis_tuser=input_2_axis_tuser,
input_3_axis_tdata=input_3_axis_tdata,
input_3_axis_tvalid=input_3_axis_tvalid,
input_3_axis_tready=input_3_axis_tready,
input_3_axis_tlast=input_3_axis_tlast,
input_3_axis_tuser=input_3_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser,
m_axis_tdata=m_axis_tdata,
m_axis_tvalid=m_axis_tvalid,
m_axis_tready=m_axis_tready,
m_axis_tlast=m_axis_tlast,
m_axis_tuser=m_axis_tuser,
tag=tag,
busy=busy
@ -229,15 +169,15 @@ def bench():
test_frame_1 = axis_ep.AXIStreamFrame(b'\x01\xAA\xBB\xCC\xDD\x01')
test_frame_2 = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
test_frame_3 = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
source_0.send(test_frame_0)
source_1.send(test_frame_1)
source_2.send(test_frame_2)
source_3.send(test_frame_3)
source_list[0].send(test_frame_0)
source_list[1].send(test_frame_1)
source_list[2].send(test_frame_2)
source_list[3].send(test_frame_3)
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data == struct.pack('>H', tag) + test_frame_0.data + test_frame_1.data + test_frame_2.data + test_frame_3.data
assert rx_frame.data == struct.pack('<H', tag) + test_frame_0.data + test_frame_1.data + test_frame_2.data + test_frame_3.data
yield delay(100)
@ -249,15 +189,15 @@ def bench():
test_frame_1 = axis_ep.AXIStreamFrame(b'\x01\xAA\xBB\xCC\xDD\x01')
test_frame_2 = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
test_frame_3 = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
source_0.send(test_frame_0)
source_1.send(test_frame_1)
source_2.send(test_frame_2)
source_3.send(test_frame_3)
source_list[0].send(test_frame_0)
source_list[1].send(test_frame_1)
source_list[2].send(test_frame_2)
source_list[3].send(test_frame_3)
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data == struct.pack('>H', tag) + test_frame_0.data + test_frame_1.data + test_frame_2.data + test_frame_3.data
assert rx_frame.data == struct.pack('<H', tag) + test_frame_0.data + test_frame_1.data + test_frame_2.data + test_frame_3.data
yield delay(100)
@ -269,18 +209,18 @@ def bench():
test_frame_1 = axis_ep.AXIStreamFrame(b'\x01\xAA\xBB\xCC\xDD\x01')
test_frame_2 = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
test_frame_3 = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
source_0.send(test_frame_0)
source_1.send(test_frame_1)
source_2.send(test_frame_2)
source_3.send(test_frame_3)
source_list[0].send(test_frame_0)
source_list[1].send(test_frame_1)
source_list[2].send(test_frame_2)
source_list[3].send(test_frame_3)
yield clk.posedge
yield delay(64)
yield clk.posedge
source_1_pause.next = True
source_pause_list[1].next = True
yield delay(32)
yield clk.posedge
source_1_pause.next = False
source_pause_list[1].next = False
yield delay(64)
yield clk.posedge
@ -292,7 +232,7 @@ def bench():
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data == struct.pack('>H', tag) + test_frame_0.data + test_frame_1.data + test_frame_2.data + test_frame_3.data
assert rx_frame.data == struct.pack('<H', tag) + test_frame_0.data + test_frame_1.data + test_frame_2.data + test_frame_3.data
yield delay(100)
@ -308,24 +248,24 @@ def bench():
test_frame_2b = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
test_frame_3a = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
test_frame_3b = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
source_0.send(test_frame_0a)
source_0.send(test_frame_0b)
source_1.send(test_frame_1a)
source_1.send(test_frame_1b)
source_2.send(test_frame_2a)
source_2.send(test_frame_2b)
source_3.send(test_frame_3a)
source_3.send(test_frame_3b)
source_list[0].send(test_frame_0a)
source_list[0].send(test_frame_0b)
source_list[1].send(test_frame_1a)
source_list[1].send(test_frame_1b)
source_list[2].send(test_frame_2a)
source_list[2].send(test_frame_2b)
source_list[3].send(test_frame_3a)
source_list[3].send(test_frame_3b)
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data == struct.pack('>H', tag) + test_frame_0a.data + test_frame_1a.data + test_frame_2a.data + test_frame_3a.data
assert rx_frame.data == struct.pack('<H', tag) + test_frame_0a.data + test_frame_1a.data + test_frame_2a.data + test_frame_3a.data
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data == struct.pack('>H', tag) + test_frame_0b.data + test_frame_1b.data + test_frame_2b.data + test_frame_3b.data
assert rx_frame.data == struct.pack('<H', tag) + test_frame_0b.data + test_frame_1b.data + test_frame_2b.data + test_frame_3b.data
yield delay(100)
@ -341,39 +281,39 @@ def bench():
test_frame_2b = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
test_frame_3a = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
test_frame_3b = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
source_0.send(test_frame_0a)
source_0.send(test_frame_0b)
source_1.send(test_frame_1a)
source_1.send(test_frame_1b)
source_2.send(test_frame_2a)
source_2.send(test_frame_2b)
source_3.send(test_frame_3a)
source_3.send(test_frame_3b)
source_list[0].send(test_frame_0a)
source_list[0].send(test_frame_0b)
source_list[1].send(test_frame_1a)
source_list[1].send(test_frame_1b)
source_list[2].send(test_frame_2a)
source_list[2].send(test_frame_2b)
source_list[3].send(test_frame_3a)
source_list[3].send(test_frame_3b)
yield clk.posedge
while input_3_axis_tvalid or output_axis_tvalid:
source_0_pause.next = True
source_1_pause.next = True
source_2_pause.next = True
source_3_pause.next = True
while s_axis_tvalid or m_axis_tvalid:
source_pause_list[0].next = True
source_pause_list[1].next = True
source_pause_list[2].next = True
source_pause_list[3].next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_0_pause.next = False
source_1_pause.next = False
source_2_pause.next = False
source_3_pause.next = False
source_pause_list[0].next = False
source_pause_list[1].next = False
source_pause_list[2].next = False
source_pause_list[3].next = False
yield clk.posedge
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data == struct.pack('>H', tag) + test_frame_0a.data + test_frame_1a.data + test_frame_2a.data + test_frame_3a.data
assert rx_frame.data == struct.pack('<H', tag) + test_frame_0a.data + test_frame_1a.data + test_frame_2a.data + test_frame_3a.data
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data == struct.pack('>H', tag) + test_frame_0b.data + test_frame_1b.data + test_frame_2b.data + test_frame_3b.data
assert rx_frame.data == struct.pack('<H', tag) + test_frame_0b.data + test_frame_1b.data + test_frame_2b.data + test_frame_3b.data
yield delay(100)
@ -389,17 +329,17 @@ def bench():
test_frame_2b = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
test_frame_3a = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
test_frame_3b = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
source_0.send(test_frame_0a)
source_0.send(test_frame_0b)
source_1.send(test_frame_1a)
source_1.send(test_frame_1b)
source_2.send(test_frame_2a)
source_2.send(test_frame_2b)
source_3.send(test_frame_3a)
source_3.send(test_frame_3b)
source_list[0].send(test_frame_0a)
source_list[0].send(test_frame_0b)
source_list[1].send(test_frame_1a)
source_list[1].send(test_frame_1b)
source_list[2].send(test_frame_2a)
source_list[2].send(test_frame_2b)
source_list[3].send(test_frame_3a)
source_list[3].send(test_frame_3b)
yield clk.posedge
while input_3_axis_tvalid or output_axis_tvalid:
while s_axis_tvalid or m_axis_tvalid:
sink_pause.next = True
yield clk.posedge
yield clk.posedge
@ -410,12 +350,12 @@ def bench():
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data == struct.pack('>H', tag) + test_frame_0a.data + test_frame_1a.data + test_frame_2a.data + test_frame_3a.data
assert rx_frame.data == struct.pack('<H', tag) + test_frame_0a.data + test_frame_1a.data + test_frame_2a.data + test_frame_3a.data
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data == struct.pack('>H', tag) + test_frame_0b.data + test_frame_1b.data + test_frame_2b.data + test_frame_3b.data
assert rx_frame.data == struct.pack('<H', tag) + test_frame_0b.data + test_frame_1b.data + test_frame_2b.data + test_frame_3b.data
yield delay(100)
@ -428,15 +368,15 @@ def bench():
test_frame_2 = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
test_frame_3 = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
test_frame_0.last_cycle_user = 1
source_0.send(test_frame_0)
source_1.send(test_frame_1)
source_2.send(test_frame_2)
source_3.send(test_frame_3)
source_list[0].send(test_frame_0)
source_list[1].send(test_frame_1)
source_list[2].send(test_frame_2)
source_list[3].send(test_frame_3)
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data == struct.pack('>H', tag) + test_frame_0.data + test_frame_1.data + test_frame_2.data + test_frame_3.data
assert rx_frame.data == struct.pack('<H', tag) + test_frame_0.data + test_frame_1.data + test_frame_2.data + test_frame_3.data
assert rx_frame.last_cycle_user
yield delay(100)

113
tb/test_axis_frame_join_4.v
View File

@ -27,11 +27,13 @@ THE SOFTWARE.
`timescale 1ns / 1ps
/*
* Testbench for axis_frame_join_4
* Testbench for axis_frame_join
*/
module test_axis_frame_join_4;
// Parameters
parameter DATA_WIDTH = 8;
parameter S_COUNT = 4;
parameter TAG_ENABLE = 1;
parameter TAG_WIDTH = 16;
@ -40,34 +42,19 @@ reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] input_0_axis_tdata = 0;
reg input_0_axis_tvalid = 0;
reg input_0_axis_tlast = 0;
reg input_0_axis_tuser = 0;
reg [7:0] input_1_axis_tdata = 0;
reg input_1_axis_tvalid = 0;
reg input_1_axis_tlast = 0;
reg input_1_axis_tuser = 0;
reg [7:0] input_2_axis_tdata = 0;
reg input_2_axis_tvalid = 0;
reg input_2_axis_tlast = 0;
reg input_2_axis_tuser = 0;
reg [7:0] input_3_axis_tdata = 0;
reg input_3_axis_tvalid = 0;
reg input_3_axis_tlast = 0;
reg input_3_axis_tuser = 0;
reg output_axis_tready = 0;
reg [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [S_COUNT-1:0] s_axis_tvalid = 0;
reg [S_COUNT-1:0] s_axis_tlast = 0;
reg [S_COUNT-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
reg [TAG_WIDTH-1:0] tag = 0;
// Outputs
wire input_0_axis_tready;
wire input_1_axis_tready;
wire input_2_axis_tready;
wire input_3_axis_tready;
wire [7:0] output_axis_tdata;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
wire [S_COUNT-1:0] s_axis_tready;
wire [7:0] m_axis_tdata;
wire m_axis_tvalid;
wire m_axis_tlast;
wire m_axis_tuser;
wire busy;
initial begin
@ -76,34 +63,19 @@ initial begin
clk,
rst,
current_test,
input_0_axis_tdata,
input_0_axis_tvalid,
input_0_axis_tlast,
input_0_axis_tuser,
input_1_axis_tdata,
input_1_axis_tvalid,
input_1_axis_tlast,
input_1_axis_tuser,
input_2_axis_tdata,
input_2_axis_tvalid,
input_2_axis_tlast,
input_2_axis_tuser,
input_3_axis_tdata,
input_3_axis_tvalid,
input_3_axis_tlast,
input_3_axis_tuser,
output_axis_tready,
s_axis_tdata,
s_axis_tvalid,
s_axis_tlast,
s_axis_tuser,
m_axis_tready,
tag
);
$to_myhdl(
input_0_axis_tready,
input_1_axis_tready,
input_2_axis_tready,
input_3_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser,
s_axis_tready,
m_axis_tdata,
m_axis_tvalid,
m_axis_tlast,
m_axis_tuser,
busy
);
@ -112,7 +84,9 @@ initial begin
$dumpvars(0, test_axis_frame_join_4);
end
axis_frame_join_4 #(
axis_frame_join #(
.DATA_WIDTH(DATA_WIDTH),
.S_COUNT(S_COUNT),
.TAG_ENABLE(TAG_ENABLE),
.TAG_WIDTH(TAG_WIDTH)
)
@ -120,32 +94,17 @@ UUT (
.clk(clk),
.rst(rst),
// axi input
.input_0_axis_tdata(input_0_axis_tdata),
.input_0_axis_tvalid(input_0_axis_tvalid),
.input_0_axis_tready(input_0_axis_tready),
.input_0_axis_tlast(input_0_axis_tlast),
.input_0_axis_tuser(input_0_axis_tuser),
.input_1_axis_tdata(input_1_axis_tdata),
.input_1_axis_tvalid(input_1_axis_tvalid),
.input_1_axis_tready(input_1_axis_tready),
.input_1_axis_tlast(input_1_axis_tlast),
.input_1_axis_tuser(input_1_axis_tuser),
.input_2_axis_tdata(input_2_axis_tdata),
.input_2_axis_tvalid(input_2_axis_tvalid),
.input_2_axis_tready(input_2_axis_tready),
.input_2_axis_tlast(input_2_axis_tlast),
.input_2_axis_tuser(input_2_axis_tuser),
.input_3_axis_tdata(input_3_axis_tdata),
.input_3_axis_tvalid(input_3_axis_tvalid),
.input_3_axis_tready(input_3_axis_tready),
.input_3_axis_tlast(input_3_axis_tlast),
.input_3_axis_tuser(input_3_axis_tuser),
.s_axis_tdata(s_axis_tdata),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tuser(s_axis_tuser),
// axi output
.output_axis_tdata(output_axis_tdata),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser),
.m_axis_tdata(m_axis_tdata),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tuser(m_axis_tuser),
// config
.tag(tag),
// status