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Code Issues Projects Releases Wiki Activity

Remove deprecated assignments

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This commit is contained in:
Alex Forencich 2022-03-15 17:52:12 -07:00
parent 1291d7b1b7
commit fdabde6d0f
11 changed files with 55 additions and 55 deletions
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4
fpga/common/tb/cmac_pad/test_cmac_pad.py
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@ -66,10 +66,10 @@ class TB(object):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)

6
fpga/common/tb/cpl_queue_manager/test_cpl_queue_manager.py
View File

@ -98,10 +98,10 @@ class TB(object):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
@ -114,7 +114,7 @@ async def run_test(dut):
await tb.reset()
dut.enable <= 1
dut.enable.value = 1
tb.log.info("Test read and write queue configuration registers")

6
fpga/common/tb/queue_manager/test_queue_manager.py
View File

@ -98,10 +98,10 @@ class TB(object):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
@ -114,7 +114,7 @@ async def run_test(dut):
await tb.reset()
dut.enable <= 1
dut.enable.value = 1
tb.log.info("Test read and write queue configuration registers")

4
fpga/common/tb/rx_checksum/test_rx_checksum.py
View File

@ -77,10 +77,10 @@ class TB(object):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)

6
fpga/common/tb/rx_hash/test_rx_hash.py
View File

@ -123,16 +123,16 @@ class TB(object):
def set_hash_key(self, key):
self.hash_key = key
self.dut.hash_key <= int.from_bytes(key, 'big')
self.dut.hash_key.value = int.from_bytes(key, 'big')
async def reset(self):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)

16
fpga/common/tb/stats_collect/test_stats_collect.py
View File

@ -67,10 +67,10 @@ class TB(object):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
@ -94,11 +94,11 @@ async def run_test_acc(dut, data_in=None, backpressure_inserter=None):
valid |= 1 << k
await RisingEdge(dut.clk)
dut.stat_inc <= inc
dut.stat_valid <= valid
dut.stat_inc.value = inc
dut.stat_valid.value = valid
await RisingEdge(dut.clk)
dut.stat_inc <= 0
dut.stat_valid <= 0
dut.stat_inc.value = 0
dut.stat_valid.value = 0
await Timer(1000, 'ns')
@ -162,8 +162,8 @@ async def run_stress_test(dut, backpressure_inserter=None):
inc |= (count) << (stat_inc_width*num)
valid |= 1 << num
dut.stat_inc <= inc
dut.stat_valid <= valid
dut.stat_inc.value = inc
dut.stat_valid.value = valid
driver = cocotb.start_soon(driver(dut, queue_drive))

4
fpga/common/tb/stats_counter/test_stats_counter.py
View File

@ -75,10 +75,10 @@ class TB(object):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)

4
fpga/common/tb/tdma_ber/test_tdma_ber.py
View File

@ -73,10 +73,10 @@ class TB(object):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)

26
fpga/common/tb/tdma_ber_ch/test_tdma_ber_ch.py
View File

@ -68,10 +68,10 @@ class TB(object):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
@ -83,14 +83,14 @@ class TB(object):
await RisingEdge(self.dut.clk)
for i in range(cycles):
for k in range(slots):
self.dut.tdma_timeslot_index <= k
self.dut.tdma_timeslot_start <= 1
self.dut.tdma_timeslot_active <= 1
self.dut.tdma_timeslot_index.value = k
self.dut.tdma_timeslot_start.value = 1
self.dut.tdma_timeslot_active.value = 1
await RisingEdge(self.dut.clk)
self.dut.tdma_timeslot_start <= 0
self.dut.tdma_timeslot_start.value = 0
for k in range(active_period-1):
await RisingEdge(self.dut.clk)
self.dut.tdma_timeslot_active <= 0
self.dut.tdma_timeslot_active.value = 0
for k in range(period-active_period):
await RisingEdge(self.dut.clk)
@ -134,12 +134,12 @@ async def run_test(dut):
await tb.clear_timeslot_counters()
await RisingEdge(dut.clk)
dut.phy_rx_error_count <= 1
dut.phy_rx_error_count.value = 1
await tb.run_scheduler(period=50, active_period=None, slots=4, cycles=5)
await RisingEdge(dut.clk)
dut.phy_rx_error_count <= 0
dut.phy_rx_error_count.value = 0
await tb.dump_counters()
await tb.dump_timeslot_counters()
@ -161,12 +161,12 @@ async def run_test(dut):
await tb.clear_timeslot_counters()
await RisingEdge(dut.clk)
dut.phy_rx_error_count <= 1
dut.phy_rx_error_count.value = 1
await tb.run_scheduler(period=50, active_period=40, slots=4, cycles=5)
await RisingEdge(dut.clk)
dut.phy_rx_error_count <= 0
dut.phy_rx_error_count.value = 0
await tb.dump_counters()
await tb.dump_timeslot_counters()
@ -194,12 +194,12 @@ async def run_test(dut):
await tb.clear_timeslot_counters(k)
await RisingEdge(dut.clk)
dut.phy_rx_error_count <= 1
dut.phy_rx_error_count.value = 1
await tb.run_scheduler(period=500, active_period=400, slots=4, cycles=5)
await RisingEdge(dut.clk)
dut.phy_rx_error_count <= 0
dut.phy_rx_error_count.value = 0
await tb.dump_counters()
for k in range(3):

30
fpga/common/tb/tdma_scheduler/test_tdma_scheduler.py
View File

@ -76,10 +76,10 @@ class TB(object):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
@ -90,27 +90,27 @@ async def run_test(dut):
await tb.reset()
dut.enable <= 1
dut.enable.value = 1
tb.log.info("Test pulse out")
await RisingEdge(dut.clk)
dut.input_schedule_start <= 1000
dut.input_schedule_start_valid <= 1
dut.input_schedule_period <= 2000
dut.input_schedule_period_valid <= 1
dut.input_timeslot_period <= 400
dut.input_timeslot_period_valid <= 1
dut.input_active_period <= 300
dut.input_active_period_valid <= 1
dut.input_schedule_start.value = 1000
dut.input_schedule_start_valid.value = 1
dut.input_schedule_period.value = 2000
dut.input_schedule_period_valid.value = 1
dut.input_timeslot_period.value = 400
dut.input_timeslot_period_valid.value = 1
dut.input_active_period.value = 300
dut.input_active_period_valid.value = 1
await RisingEdge(dut.clk)
dut.input_schedule_start_valid <= 0
dut.input_schedule_period_valid <= 0
dut.input_timeslot_period_valid <= 0
dut.input_active_period_valid <= 0
dut.input_schedule_start_valid.value = 0
dut.input_schedule_period_valid.value = 0
dut.input_timeslot_period_valid.value = 0
dut.input_active_period_valid.value = 0
await Timer(10000, 'ns')

4
fpga/common/tb/tx_checksum/test_tx_checksum.py
View File

@ -85,10 +85,10 @@ class TB(object):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 1
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst <= 0
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)