From fe7396a31e29e97f571d90894b6fb54a17072e65 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Wed, 22 Aug 2018 21:55:08 -0700 Subject: [PATCH] Update readme --- README.md | 142 +++++++++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 134 insertions(+), 8 deletions(-) diff --git a/README.md b/README.md index 62d23d5c7..c51ba2c4b 100644 --- a/README.md +++ b/README.md @@ -6,16 +6,115 @@ GitHub repository: https://github.com/alexforencich/verilog-axi ## Introduction -Collection of AXI4 bus components. Most components are fully parametrizable -in interface widths. Includes full MyHDL testbench with intelligent bus -cosimulation endpoints. +Collection of AXI4 and AXI4 lite bus components. Most components are fully +parametrizable in interface widths. Includes full MyHDL testbench with +intelligent bus cosimulation endpoints. ## Documentation +### axi_adapter module + +AXI width adapter module with parametrizable data and address interface widths. +Supports INCR burst types and narrow bursts. Wrapper for axi_adapter_rd and axi_adapter_wr. + +### axi_adapter_rd module + +AXI width adapter module with parametrizable data and address interface widths. +Supports INCR burst types and narrow bursts. + +### axi_adapter_wr module + +AXI width adapter module with parametrizable data and address interface widths. +Supports INCR burst types and narrow bursts. + +### axi_fifo module + +AXI FIFO with parametrizable data and address interface widths. Supports all +burst types. Optionally can delay the address channel until either the write +data is completely shifted into the FIFO or the read data FIFO has enough +capacity to fit the whole burst. Wrapper for axi_fifo_rd and axi_fifo_wr. + +### axi_fifo_rd module + +AXI FIFO with parametrizable data and address interface widths. AR and R +channels only. Supports all burst types. Optionally can delay the address +channel until either the read data FIFO is empty or has enough capacity to fit +the whole burst. + +### axi_fifo_wr module + +AXI FIFO with parametrizable data and address interface widths. WR, W, and B +channels only. Supports all burst types. Optionally can delay the address +channel until the write data is shifted completely into the write data FIFO, +or the current burst completely fills the write data FIFO. + ### axi_ram module -RAM with parametrizable data and address interface widths. Supports FIXED and -INCR burst types as well as narrow bursts. +AXI RAM with parametrizable data and address interface widths. Supports FIXED +and INCR burst types as well as narrow bursts. + +### axi_register module + +AXI register with parametrizable data and address interface widths. Supports +all burst types. Inserts simple buffers or skid buffers into all channels. +Channel register types can be individually changed or bypassed. Wrapper for +axi_register_rd and axi_register_wr. + +### axi_register_rd module + +AXI register with parametrizable data and address interface widths. AR and R +channels only. Supports all burst types. Inserts simple buffers or skid +buffers into all channels. Channel register types can be individually changed +or bypassed. + +### axi_register_wr module + +AXI register with parametrizable data and address interface widths. WR, W, +and B channels only. Supports all burst types. Inserts simple buffers or +skid buffers into all channels. Channel register types can be individually +changed or bypassed. + +### axil_adapter module + +AXI lite width adapter module with parametrizable data and address interface +widths. Wrapper for axi_adapter_rd and axi_adapter_wr. + +### axil_adapter_rd module + +AXI lite width adapter module with parametrizable data and address interface +widths. + +### axil_adapter_wr module + +AXI lite width adapter module with parametrizable data and address interface +widths. + +### axil_interconnect module + +AXI lite shared interconnect with parametrizable data and address interface +widths. Small in area, but does not support concurrent operations. + +### axil_ram module + +AXI lite RAM with parametrizable data and address interface widths. + +### axil_register module + +AXI lite register with parametrizable data and address interface widths. +Inserts skid buffers into all channels. Channel registers can be individually +bypassed. Wrapper for axil_register_rd and axil_register_wr. + +### axil_register_rd module + +AXI lite register with parametrizable data and address interface widths. AR +and R channels only. Inserts simple buffers into all channels. Channel +registers can be individually bypassed. + +### axil_register_wr module + +AXI lite register with parametrizable data and address interface widths. WR, +W, and B channels only. Inserts simple buffers into all channels. Channel +registers can be individually bypassed. ### Common signals @@ -65,17 +164,43 @@ INCR burst types as well as narrow bursts. rready : Read response ready (from master) ### Common parameters - + ADDR_WIDTH : width of awaddr and araddr signals DATA_WIDTH : width of wdata and rdata signals STRB_WIDTH : width of wstrb signal ID_WIDTH : width of *id signals - USER_WIDTH : width of *user signals + AWUSER_ENABLE : enable awuser signal + AWUSER_WIDTH : width of awuser signal + WUSER_ENABLE : enable wuser signal + WUSER_WIDTH : width of wuser signal + BUSER_ENABLE : enable buser signal + BUSER_WIDTH : width of buser signal + ARUSER_ENABLE : enable aruser signal + ARUSER_WIDTH : width of aruser signal + RUSER_ENABLE : enable ruser signal + RUSER_WIDTH : width of ruser signal ### Source Files rtl/arbiter.v : Parametrizable arbiter - rtl/axi_ram.v : Parametrizable AXI RAM + rtl/axi_adapter.v : AXI lite width converter + rtl/axi_adapter_rd.v : AXI lite width converter (read) + rtl/axi_adapter_wr.v : AXI lite width converter (write) + rtl/axi_fifo.v : AXI FIFO + rtl/axi_fifo_rd.v : AXI FIFO (read) + rtl/axi_fifo_wr.v : AXI FIFO (write) + rtl/axi_ram.v : AXI RAM + rtl/axi_register.v : AXI register + rtl/axi_register_rd.v : AXI register (read) + rtl/axi_register_wr.v : AXI register (write) + rtl/axil_adapter.v : AXI lite width converter + rtl/axil_adapter_rd.v : AXI lite width converter (read) + rtl/axil_adapter_wr.v : AXI lite width converter (write) + rtl/axil_interconnect.v : AXI lite interconnect + rtl/axil_ram.v : AXI lite RAM + rtl/axil_register.v : AXI lite register + rtl/axil_register_rd.v : AXI lite register (read) + rtl/axil_register_wr.v : AXI lite register (write) rtl/priority_encoder.v : Parametrizable priority encoder ### AXI4-Lite Interface Example @@ -160,3 +285,4 @@ individual test scripts can be run with python directly. ### Testbench Files tb/axi.py : MyHDL AXI4 master and memory BFM + tb/axil.py : MyHDL AXI4 lite master and memory BFM