From ffd04d2bb006f35fbd672aed7f1c780aebf89696 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Tue, 28 Jul 2020 19:00:33 -0700 Subject: [PATCH] Cleanup --- .../fpga_100g/tb/test_fpga_core.py | 10 ------ .../fpga_10g/tb/test_fpga_core.py | 10 ------ .../fpga_25g/tb/test_fpga_core.py | 10 ------ .../AU280/fpga_100g/tb/test_fpga_core.py | 10 ------ .../mqnic/AU280/fpga_10g/tb/test_fpga_core.py | 10 ------ .../mqnic/AU50/fpga_100g/tb/test_fpga_core.py | 10 ------ fpga/mqnic/AU50/fpga_10g/tb/test_fpga_core.py | 10 ------ .../ExaNIC_X10/fpga/tb/test_fpga_core.py | 36 +++++++++---------- .../ExaNIC_X25/fpga_10g/tb/test_fpga_core.py | 3 -- .../VCU108/fpga_10g/tb/test_fpga_core.py | 3 -- .../VCU118/fpga_100g/tb/test_fpga_core.py | 10 ------ .../VCU118/fpga_10g/tb/test_fpga_core.py | 10 ------ .../VCU1525/fpga_100g/tb/test_fpga_core.py | 10 ------ .../VCU1525/fpga_10g/tb/test_fpga_core.py | 10 ------ .../fpga_10g/tb/test_fpga_core.py | 10 ------ .../ExaNIC_X10/fpga/tb/test_fpga_core.py | 3 -- .../VCU108/fpga_10g/tb/test_fpga_core.py | 3 -- .../VCU118/fpga_10g/tb/test_fpga_core.py | 10 ------ 18 files changed, 18 insertions(+), 160 deletions(-) diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/test_fpga_core.py b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/test_fpga_core.py index 5e2ca6b40..c6cbf4223 100755 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/test_fpga_core.py +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/test_fpga_core.py @@ -745,22 +745,12 @@ def bench(): yield rc.enumerate(enable_bus_mastering=True, configure_msi=True) - dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc - dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc - yield delay(100) yield clk.posedge print("test 2: init NIC") current_test.next = 2 - #data = yield from rc.mem_read(dev_pf0_bar0+0x20000+0x10, 4); - #print(data) - - #yield delay(1000) - - #raise StopSimulation - yield from driver.init_dev(dev.functions[0].get_id()) yield from driver.interfaces[0].open() #yield from driver.interfaces[1].open() diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py b/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py index bde164777..7a16604d7 100755 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py @@ -865,22 +865,12 @@ def bench(): yield rc.enumerate(enable_bus_mastering=True, configure_msi=True) - dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc - dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc - yield delay(100) yield clk.posedge print("test 2: init NIC") current_test.next = 2 - #data = yield from rc.mem_read(dev_pf0_bar0+0x20000+0x10, 4); - #print(data) - - #yield delay(1000) - - #raise StopSimulation - yield from driver.init_dev(dev.functions[0].get_id()) yield from driver.interfaces[0].open() #yield from driver.interfaces[1].open() diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/test_fpga_core.py b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/test_fpga_core.py index e8087324e..93d666696 100755 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/test_fpga_core.py +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/test_fpga_core.py @@ -865,22 +865,12 @@ def bench(): yield rc.enumerate(enable_bus_mastering=True, configure_msi=True) - dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc - dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc - yield delay(100) yield clk.posedge print("test 2: init NIC") current_test.next = 2 - #data = yield from rc.mem_read(dev_pf0_bar0+0x20000+0x10, 4); - #print(data) - - #yield delay(1000) - - #raise StopSimulation - yield from driver.init_dev(dev.functions[0].get_id()) yield from driver.interfaces[0].open() #yield from driver.interfaces[1].open() diff --git a/fpga/mqnic/AU280/fpga_100g/tb/test_fpga_core.py b/fpga/mqnic/AU280/fpga_100g/tb/test_fpga_core.py index f5fd7a10b..732ae1559 100755 --- a/fpga/mqnic/AU280/fpga_100g/tb/test_fpga_core.py +++ b/fpga/mqnic/AU280/fpga_100g/tb/test_fpga_core.py @@ -681,22 +681,12 @@ def bench(): yield rc.enumerate(enable_bus_mastering=True, configure_msi=True) - dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc - dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc - yield delay(100) yield clk.posedge print("test 2: init NIC") current_test.next = 2 - #data = yield from rc.mem_read(dev_pf0_bar0+0x20000+0x10, 4); - #print(data) - - #yield delay(1000) - - #raise StopSimulation - yield from driver.init_dev(dev.functions[0].get_id()) yield from driver.interfaces[0].open() #yield from driver.interfaces[1].open() diff --git a/fpga/mqnic/AU280/fpga_10g/tb/test_fpga_core.py b/fpga/mqnic/AU280/fpga_10g/tb/test_fpga_core.py index 9cd82895f..0865033ce 100755 --- a/fpga/mqnic/AU280/fpga_10g/tb/test_fpga_core.py +++ b/fpga/mqnic/AU280/fpga_10g/tb/test_fpga_core.py @@ -796,22 +796,12 @@ def bench(): yield rc.enumerate(enable_bus_mastering=True, configure_msi=True) - dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc - dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc - yield delay(100) yield clk.posedge print("test 2: init NIC") current_test.next = 2 - #data = yield from rc.mem_read(dev_pf0_bar0+0x20000+0x10, 4); - #print(data) - - #yield delay(1000) - - #raise StopSimulation - yield from driver.init_dev(dev.functions[0].get_id()) yield from driver.interfaces[0].open() #yield from driver.interfaces[1].open() diff --git a/fpga/mqnic/AU50/fpga_100g/tb/test_fpga_core.py b/fpga/mqnic/AU50/fpga_100g/tb/test_fpga_core.py index 9c555355d..9bbfcdb2e 100755 --- a/fpga/mqnic/AU50/fpga_100g/tb/test_fpga_core.py +++ b/fpga/mqnic/AU50/fpga_100g/tb/test_fpga_core.py @@ -617,22 +617,12 @@ def bench(): yield rc.enumerate(enable_bus_mastering=True, configure_msi=True) - dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc - dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc - yield delay(100) yield clk.posedge print("test 2: init NIC") current_test.next = 2 - #data = yield from rc.mem_read(dev_pf0_bar0+0x20000+0x10, 4); - #print(data) - - #yield delay(1000) - - #raise StopSimulation - yield from driver.init_dev(dev.functions[0].get_id()) yield from driver.interfaces[0].open() #yield from driver.interfaces[1].open() diff --git a/fpga/mqnic/AU50/fpga_10g/tb/test_fpga_core.py b/fpga/mqnic/AU50/fpga_10g/tb/test_fpga_core.py index e6043708c..3a9f6a37f 100755 --- a/fpga/mqnic/AU50/fpga_10g/tb/test_fpga_core.py +++ b/fpga/mqnic/AU50/fpga_10g/tb/test_fpga_core.py @@ -678,22 +678,12 @@ def bench(): yield rc.enumerate(enable_bus_mastering=True, configure_msi=True) - dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc - dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc - yield delay(100) yield clk.posedge print("test 2: init NIC") current_test.next = 2 - #data = yield from rc.mem_read(dev_pf0_bar0+0x20000+0x10, 4); - #print(data) - - #yield delay(1000) - - #raise StopSimulation - yield from driver.init_dev(dev.functions[0].get_id()) yield from driver.interfaces[0].open() #yield from driver.interfaces[1].open() diff --git a/fpga/mqnic/ExaNIC_X10/fpga/tb/test_fpga_core.py b/fpga/mqnic/ExaNIC_X10/fpga/tb/test_fpga_core.py index 453ce99ff..dbdfdfc3b 100755 --- a/fpga/mqnic/ExaNIC_X10/fpga/tb/test_fpga_core.py +++ b/fpga/mqnic/ExaNIC_X10/fpga/tb/test_fpga_core.py @@ -649,24 +649,6 @@ def bench(): yield rc.enumerate(enable_bus_mastering=True, configure_msi=True) - dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc - dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc - - yield from rc.mem_write_dword(dev_pf0_bar0+0x270, 0); - yield from rc.mem_write_dword(dev_pf0_bar0+0x274, 0); - yield from rc.mem_write_dword(dev_pf0_bar0+0x278, 0); - yield from rc.mem_write_dword(dev_pf0_bar0+0x27C, 0); - - yield from rc.mem_write_dword(dev_pf0_bar0+0x290, 0); - yield from rc.mem_write_dword(dev_pf0_bar0+0x294, 1000); - yield from rc.mem_write_dword(dev_pf0_bar0+0x298, 0); - yield from rc.mem_write_dword(dev_pf0_bar0+0x29C, 0); - - yield from rc.mem_write_dword(dev_pf0_bar0+0x280, 0); - yield from rc.mem_write_dword(dev_pf0_bar0+0x284, 2000); - yield from rc.mem_write_dword(dev_pf0_bar0+0x288, 0); - yield from rc.mem_write_dword(dev_pf0_bar0+0x28C, 0); - yield delay(100) yield clk.posedge @@ -683,6 +665,24 @@ def bench(): yield from rc.mem_read(driver.hw_addr, 4) # wait for all writes to complete + # configure PTP period out + yield from rc.mem_write_dword(driver.hw_addr+0x270, 0) # start fns + yield from rc.mem_write_dword(driver.hw_addr+0x274, 0) # start ns + yield from rc.mem_write_dword(driver.hw_addr+0x278, 0) # start sec (low) + yield from rc.mem_write_dword(driver.hw_addr+0x27C, 0) # start sec (high) + + yield from rc.mem_write_dword(driver.hw_addr+0x290, 0) # width fns + yield from rc.mem_write_dword(driver.hw_addr+0x294, 1000) # width ns + yield from rc.mem_write_dword(driver.hw_addr+0x298, 0) # width sec (low) + yield from rc.mem_write_dword(driver.hw_addr+0x29C, 0) # width sec (high) + + yield from rc.mem_write_dword(driver.hw_addr+0x280, 0) # period fns + yield from rc.mem_write_dword(driver.hw_addr+0x284, 2000) # period ns + yield from rc.mem_write_dword(driver.hw_addr+0x288, 0) # period sec (low) + yield from rc.mem_write_dword(driver.hw_addr+0x28C, 0) # period sec (high) + + yield from rc.mem_write_dword(driver.hw_addr+0x260, 1) # enable output + yield delay(100) yield clk.posedge diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/test_fpga_core.py b/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/test_fpga_core.py index f62d60329..0eb1a8bff 100755 --- a/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/test_fpga_core.py +++ b/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/test_fpga_core.py @@ -656,9 +656,6 @@ def bench(): yield rc.enumerate(enable_bus_mastering=True, configure_msi=True) - dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc - dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc - yield delay(100) yield clk.posedge diff --git a/fpga/mqnic/VCU108/fpga_10g/tb/test_fpga_core.py b/fpga/mqnic/VCU108/fpga_10g/tb/test_fpga_core.py index 5ec0b6fa1..65ce7a367 100755 --- a/fpga/mqnic/VCU108/fpga_10g/tb/test_fpga_core.py +++ b/fpga/mqnic/VCU108/fpga_10g/tb/test_fpga_core.py @@ -719,9 +719,6 @@ def bench(): yield rc.enumerate(enable_bus_mastering=True, configure_msi=True) - dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc - dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc - yield delay(100) yield clk.posedge diff --git a/fpga/mqnic/VCU118/fpga_100g/tb/test_fpga_core.py b/fpga/mqnic/VCU118/fpga_100g/tb/test_fpga_core.py index 9e94f681c..dc801165d 100755 --- a/fpga/mqnic/VCU118/fpga_100g/tb/test_fpga_core.py +++ b/fpga/mqnic/VCU118/fpga_100g/tb/test_fpga_core.py @@ -728,22 +728,12 @@ def bench(): yield rc.enumerate() - dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc - dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc - yield delay(100) yield clk.posedge print("test 2: init NIC") current_test.next = 2 - #data = yield from rc.mem_read(dev_pf0_bar0+0x20000+0x10, 4); - #print(data) - - #yield delay(1000) - - #raise StopSimulation - yield from driver.init_dev(dev.functions[0].get_id()) yield from driver.interfaces[0].open() #yield from driver.interfaces[1].open() diff --git a/fpga/mqnic/VCU118/fpga_10g/tb/test_fpga_core.py b/fpga/mqnic/VCU118/fpga_10g/tb/test_fpga_core.py index 2f2e98981..f2c72c8ed 100755 --- a/fpga/mqnic/VCU118/fpga_10g/tb/test_fpga_core.py +++ b/fpga/mqnic/VCU118/fpga_10g/tb/test_fpga_core.py @@ -847,22 +847,12 @@ def bench(): yield rc.enumerate(enable_bus_mastering=True, configure_msi=True) - dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc - dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc - yield delay(100) yield clk.posedge print("test 2: init NIC") current_test.next = 2 - #data = yield from rc.mem_read(dev_pf0_bar0+0x20000+0x10, 4); - #print(data) - - #yield delay(1000) - - #raise StopSimulation - yield from driver.init_dev(dev.functions[0].get_id()) yield from driver.interfaces[0].open() #yield from driver.interfaces[1].open() diff --git a/fpga/mqnic/VCU1525/fpga_100g/tb/test_fpga_core.py b/fpga/mqnic/VCU1525/fpga_100g/tb/test_fpga_core.py index 052a824c1..bbd8f4ce0 100755 --- a/fpga/mqnic/VCU1525/fpga_100g/tb/test_fpga_core.py +++ b/fpga/mqnic/VCU1525/fpga_100g/tb/test_fpga_core.py @@ -716,22 +716,12 @@ def bench(): yield rc.enumerate(enable_bus_mastering=True, configure_msi=True) - dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc - dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc - yield delay(100) yield clk.posedge print("test 2: init NIC") current_test.next = 2 - #data = yield from rc.mem_read(dev_pf0_bar0+0x20000+0x10, 4); - #print(data) - - #yield delay(1000) - - #raise StopSimulation - yield from driver.init_dev(dev.functions[0].get_id()) yield from driver.interfaces[0].open() #yield from driver.interfaces[1].open() diff --git a/fpga/mqnic/VCU1525/fpga_10g/tb/test_fpga_core.py b/fpga/mqnic/VCU1525/fpga_10g/tb/test_fpga_core.py index 4b0737d0e..771b90af8 100755 --- a/fpga/mqnic/VCU1525/fpga_10g/tb/test_fpga_core.py +++ b/fpga/mqnic/VCU1525/fpga_10g/tb/test_fpga_core.py @@ -832,22 +832,12 @@ def bench(): yield rc.enumerate(enable_bus_mastering=True, configure_msi=True) - dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc - dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc - yield delay(100) yield clk.posedge print("test 2: init NIC") current_test.next = 2 - #data = yield from rc.mem_read(dev_pf0_bar0+0x20000+0x10, 4); - #print(data) - - #yield delay(1000) - - #raise StopSimulation - yield from driver.init_dev(dev.functions[0].get_id()) yield from driver.interfaces[0].open() #yield from driver.interfaces[1].open() diff --git a/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py b/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py index 190e75457..8d7e90073 100755 --- a/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py +++ b/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py @@ -866,22 +866,12 @@ def bench(): yield rc.enumerate(enable_bus_mastering=True, configure_msi=True) - dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc - dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc - yield delay(100) yield clk.posedge print("test 2: init NIC") current_test.next = 2 - #data = yield from rc.mem_read(dev_pf0_bar0+0x20000+0x10, 4); - #print(data) - - #yield delay(1000) - - #raise StopSimulation - yield from driver.init_dev(dev.functions[0].get_id()) yield from driver.interfaces[0].open() #yield from driver.interfaces[1].open() diff --git a/fpga/mqnic_tdma/ExaNIC_X10/fpga/tb/test_fpga_core.py b/fpga/mqnic_tdma/ExaNIC_X10/fpga/tb/test_fpga_core.py index f01954dc4..2cf3bc11d 100755 --- a/fpga/mqnic_tdma/ExaNIC_X10/fpga/tb/test_fpga_core.py +++ b/fpga/mqnic_tdma/ExaNIC_X10/fpga/tb/test_fpga_core.py @@ -650,9 +650,6 @@ def bench(): yield rc.enumerate(enable_bus_mastering=True, configure_msi=True) - dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc - dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc - yield delay(100) yield clk.posedge diff --git a/fpga/mqnic_tdma/VCU108/fpga_10g/tb/test_fpga_core.py b/fpga/mqnic_tdma/VCU108/fpga_10g/tb/test_fpga_core.py index 2eca3c051..ffc8a6de5 100755 --- a/fpga/mqnic_tdma/VCU108/fpga_10g/tb/test_fpga_core.py +++ b/fpga/mqnic_tdma/VCU108/fpga_10g/tb/test_fpga_core.py @@ -720,9 +720,6 @@ def bench(): yield rc.enumerate(enable_bus_mastering=True, configure_msi=True) - dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc - dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc - yield delay(100) yield clk.posedge diff --git a/fpga/mqnic_tdma/VCU118/fpga_10g/tb/test_fpga_core.py b/fpga/mqnic_tdma/VCU118/fpga_10g/tb/test_fpga_core.py index 3688729b9..d4b4f8926 100755 --- a/fpga/mqnic_tdma/VCU118/fpga_10g/tb/test_fpga_core.py +++ b/fpga/mqnic_tdma/VCU118/fpga_10g/tb/test_fpga_core.py @@ -848,22 +848,12 @@ def bench(): yield rc.enumerate(enable_bus_mastering=True, configure_msi=True) - dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc - dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc - yield delay(100) yield clk.posedge print("test 2: init NIC") current_test.next = 2 - #data = yield from rc.mem_read(dev_pf0_bar0+0x20000+0x10, 4); - #print(data) - - #yield delay(1000) - - #raise StopSimulation - yield from driver.init_dev(dev.functions[0].get_id()) yield from driver.interfaces[0].open() #yield from driver.interfaces[1].open()