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Code Issues Projects Releases Wiki Activity

Cleanup

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This commit is contained in:
Alex Forencich 2020-07-28 19:00:33 -07:00
parent 495178e1dc
commit ffd04d2bb0
18 changed files with 18 additions and 160 deletions
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10
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/test_fpga_core.py
View File

@ -745,22 +745,12 @@ def bench():
yield rc.enumerate(enable_bus_mastering=True, configure_msi=True)
dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc
dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc
yield delay(100)
yield clk.posedge
print("test 2: init NIC")
current_test.next = 2
#data = yield from rc.mem_read(dev_pf0_bar0+0x20000+0x10, 4);
#print(data)
#yield delay(1000)
#raise StopSimulation
yield from driver.init_dev(dev.functions[0].get_id())
yield from driver.interfaces[0].open()
#yield from driver.interfaces[1].open()

10
fpga/mqnic/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py
View File

@ -865,22 +865,12 @@ def bench():
yield rc.enumerate(enable_bus_mastering=True, configure_msi=True)
dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc
dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc
yield delay(100)
yield clk.posedge
print("test 2: init NIC")
current_test.next = 2
#data = yield from rc.mem_read(dev_pf0_bar0+0x20000+0x10, 4);
#print(data)
#yield delay(1000)
#raise StopSimulation
yield from driver.init_dev(dev.functions[0].get_id())
yield from driver.interfaces[0].open()
#yield from driver.interfaces[1].open()

10
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/test_fpga_core.py
View File

@ -865,22 +865,12 @@ def bench():
yield rc.enumerate(enable_bus_mastering=True, configure_msi=True)
dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc
dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc
yield delay(100)
yield clk.posedge
print("test 2: init NIC")
current_test.next = 2
#data = yield from rc.mem_read(dev_pf0_bar0+0x20000+0x10, 4);
#print(data)
#yield delay(1000)
#raise StopSimulation
yield from driver.init_dev(dev.functions[0].get_id())
yield from driver.interfaces[0].open()
#yield from driver.interfaces[1].open()

10
fpga/mqnic/AU280/fpga_100g/tb/test_fpga_core.py
View File

@ -681,22 +681,12 @@ def bench():
yield rc.enumerate(enable_bus_mastering=True, configure_msi=True)
dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc
dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc
yield delay(100)
yield clk.posedge
print("test 2: init NIC")
current_test.next = 2
#data = yield from rc.mem_read(dev_pf0_bar0+0x20000+0x10, 4);
#print(data)
#yield delay(1000)
#raise StopSimulation
yield from driver.init_dev(dev.functions[0].get_id())
yield from driver.interfaces[0].open()
#yield from driver.interfaces[1].open()

10
fpga/mqnic/AU280/fpga_10g/tb/test_fpga_core.py
View File

@ -796,22 +796,12 @@ def bench():
yield rc.enumerate(enable_bus_mastering=True, configure_msi=True)
dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc
dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc
yield delay(100)
yield clk.posedge
print("test 2: init NIC")
current_test.next = 2
#data = yield from rc.mem_read(dev_pf0_bar0+0x20000+0x10, 4);
#print(data)
#yield delay(1000)
#raise StopSimulation
yield from driver.init_dev(dev.functions[0].get_id())
yield from driver.interfaces[0].open()
#yield from driver.interfaces[1].open()

10
fpga/mqnic/AU50/fpga_100g/tb/test_fpga_core.py
View File

@ -617,22 +617,12 @@ def bench():
yield rc.enumerate(enable_bus_mastering=True, configure_msi=True)
dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc
dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc
yield delay(100)
yield clk.posedge
print("test 2: init NIC")
current_test.next = 2
#data = yield from rc.mem_read(dev_pf0_bar0+0x20000+0x10, 4);
#print(data)
#yield delay(1000)
#raise StopSimulation
yield from driver.init_dev(dev.functions[0].get_id())
yield from driver.interfaces[0].open()
#yield from driver.interfaces[1].open()

10
fpga/mqnic/AU50/fpga_10g/tb/test_fpga_core.py
View File

@ -678,22 +678,12 @@ def bench():
yield rc.enumerate(enable_bus_mastering=True, configure_msi=True)
dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc
dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc
yield delay(100)
yield clk.posedge
print("test 2: init NIC")
current_test.next = 2
#data = yield from rc.mem_read(dev_pf0_bar0+0x20000+0x10, 4);
#print(data)
#yield delay(1000)
#raise StopSimulation
yield from driver.init_dev(dev.functions[0].get_id())
yield from driver.interfaces[0].open()
#yield from driver.interfaces[1].open()

36
fpga/mqnic/ExaNIC_X10/fpga/tb/test_fpga_core.py
View File

@ -649,24 +649,6 @@ def bench():
yield rc.enumerate(enable_bus_mastering=True, configure_msi=True)
dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc
dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc
yield from rc.mem_write_dword(dev_pf0_bar0+0x270, 0);
yield from rc.mem_write_dword(dev_pf0_bar0+0x274, 0);
yield from rc.mem_write_dword(dev_pf0_bar0+0x278, 0);
yield from rc.mem_write_dword(dev_pf0_bar0+0x27C, 0);
yield from rc.mem_write_dword(dev_pf0_bar0+0x290, 0);
yield from rc.mem_write_dword(dev_pf0_bar0+0x294, 1000);
yield from rc.mem_write_dword(dev_pf0_bar0+0x298, 0);
yield from rc.mem_write_dword(dev_pf0_bar0+0x29C, 0);
yield from rc.mem_write_dword(dev_pf0_bar0+0x280, 0);
yield from rc.mem_write_dword(dev_pf0_bar0+0x284, 2000);
yield from rc.mem_write_dword(dev_pf0_bar0+0x288, 0);
yield from rc.mem_write_dword(dev_pf0_bar0+0x28C, 0);
yield delay(100)
yield clk.posedge
@ -683,6 +665,24 @@ def bench():
yield from rc.mem_read(driver.hw_addr, 4) # wait for all writes to complete
# configure PTP period out
yield from rc.mem_write_dword(driver.hw_addr+0x270, 0) # start fns
yield from rc.mem_write_dword(driver.hw_addr+0x274, 0) # start ns
yield from rc.mem_write_dword(driver.hw_addr+0x278, 0) # start sec (low)
yield from rc.mem_write_dword(driver.hw_addr+0x27C, 0) # start sec (high)
yield from rc.mem_write_dword(driver.hw_addr+0x290, 0) # width fns
yield from rc.mem_write_dword(driver.hw_addr+0x294, 1000) # width ns
yield from rc.mem_write_dword(driver.hw_addr+0x298, 0) # width sec (low)
yield from rc.mem_write_dword(driver.hw_addr+0x29C, 0) # width sec (high)
yield from rc.mem_write_dword(driver.hw_addr+0x280, 0) # period fns
yield from rc.mem_write_dword(driver.hw_addr+0x284, 2000) # period ns
yield from rc.mem_write_dword(driver.hw_addr+0x288, 0) # period sec (low)
yield from rc.mem_write_dword(driver.hw_addr+0x28C, 0) # period sec (high)
yield from rc.mem_write_dword(driver.hw_addr+0x260, 1) # enable output
yield delay(100)
yield clk.posedge

3
fpga/mqnic/ExaNIC_X25/fpga_10g/tb/test_fpga_core.py
View File

@ -656,9 +656,6 @@ def bench():
yield rc.enumerate(enable_bus_mastering=True, configure_msi=True)
dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc
dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc
yield delay(100)
yield clk.posedge

3
fpga/mqnic/VCU108/fpga_10g/tb/test_fpga_core.py
View File

@ -719,9 +719,6 @@ def bench():
yield rc.enumerate(enable_bus_mastering=True, configure_msi=True)
dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc
dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc
yield delay(100)
yield clk.posedge

10
fpga/mqnic/VCU118/fpga_100g/tb/test_fpga_core.py
View File

@ -728,22 +728,12 @@ def bench():
yield rc.enumerate()
dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc
dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc
yield delay(100)
yield clk.posedge
print("test 2: init NIC")
current_test.next = 2
#data = yield from rc.mem_read(dev_pf0_bar0+0x20000+0x10, 4);
#print(data)
#yield delay(1000)
#raise StopSimulation
yield from driver.init_dev(dev.functions[0].get_id())
yield from driver.interfaces[0].open()
#yield from driver.interfaces[1].open()

10
fpga/mqnic/VCU118/fpga_10g/tb/test_fpga_core.py
View File

@ -847,22 +847,12 @@ def bench():
yield rc.enumerate(enable_bus_mastering=True, configure_msi=True)
dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc
dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc
yield delay(100)
yield clk.posedge
print("test 2: init NIC")
current_test.next = 2
#data = yield from rc.mem_read(dev_pf0_bar0+0x20000+0x10, 4);
#print(data)
#yield delay(1000)
#raise StopSimulation
yield from driver.init_dev(dev.functions[0].get_id())
yield from driver.interfaces[0].open()
#yield from driver.interfaces[1].open()

10
fpga/mqnic/VCU1525/fpga_100g/tb/test_fpga_core.py
View File

@ -716,22 +716,12 @@ def bench():
yield rc.enumerate(enable_bus_mastering=True, configure_msi=True)
dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc
dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc
yield delay(100)
yield clk.posedge
print("test 2: init NIC")
current_test.next = 2
#data = yield from rc.mem_read(dev_pf0_bar0+0x20000+0x10, 4);
#print(data)
#yield delay(1000)
#raise StopSimulation
yield from driver.init_dev(dev.functions[0].get_id())
yield from driver.interfaces[0].open()
#yield from driver.interfaces[1].open()

10
fpga/mqnic/VCU1525/fpga_10g/tb/test_fpga_core.py
View File

@ -832,22 +832,12 @@ def bench():
yield rc.enumerate(enable_bus_mastering=True, configure_msi=True)
dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc
dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc
yield delay(100)
yield clk.posedge
print("test 2: init NIC")
current_test.next = 2
#data = yield from rc.mem_read(dev_pf0_bar0+0x20000+0x10, 4);
#print(data)
#yield delay(1000)
#raise StopSimulation
yield from driver.init_dev(dev.functions[0].get_id())
yield from driver.interfaces[0].open()
#yield from driver.interfaces[1].open()

10
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py
View File

@ -866,22 +866,12 @@ def bench():
yield rc.enumerate(enable_bus_mastering=True, configure_msi=True)
dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc
dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc
yield delay(100)
yield clk.posedge
print("test 2: init NIC")
current_test.next = 2
#data = yield from rc.mem_read(dev_pf0_bar0+0x20000+0x10, 4);
#print(data)
#yield delay(1000)
#raise StopSimulation
yield from driver.init_dev(dev.functions[0].get_id())
yield from driver.interfaces[0].open()
#yield from driver.interfaces[1].open()

3
fpga/mqnic_tdma/ExaNIC_X10/fpga/tb/test_fpga_core.py
View File

@ -650,9 +650,6 @@ def bench():
yield rc.enumerate(enable_bus_mastering=True, configure_msi=True)
dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc
dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc
yield delay(100)
yield clk.posedge

3
fpga/mqnic_tdma/VCU108/fpga_10g/tb/test_fpga_core.py
View File

@ -720,9 +720,6 @@ def bench():
yield rc.enumerate(enable_bus_mastering=True, configure_msi=True)
dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc
dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc
yield delay(100)
yield clk.posedge

10
fpga/mqnic_tdma/VCU118/fpga_10g/tb/test_fpga_core.py
View File

@ -848,22 +848,12 @@ def bench():
yield rc.enumerate(enable_bus_mastering=True, configure_msi=True)
dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc
dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc
yield delay(100)
yield clk.posedge
print("test 2: init NIC")
current_test.next = 2
#data = yield from rc.mem_read(dev_pf0_bar0+0x20000+0x10, 4);
#print(data)
#yield delay(1000)
#raise StopSimulation
yield from driver.init_dev(dev.functions[0].get_id())
yield from driver.interfaces[0].open()
#yield from driver.interfaces[1].open()