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Author SHA1 Message Date
Alex Forencich
1ca0151b97 merged changes in eth 2023-12-02 01:30:49 -08:00
Alex Forencich
dce0c92a57 Rework PHC to register shared adder outputs for improved timing performance 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-12-02 00:53:02 -08:00
Alex Forencich
dd97924714 Prevent stale data frim being used to sync leaf clock 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-12-01 22:05:53 -08:00
Alex Forencich
f0c47db509 Improve tolerance of sample point synchronization 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-12-01 22:03:14 -08:00
Alex Forencich
a2294c56a5 Rewrite gain scheduling 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-12-01 22:02:40 -08:00
Alex Forencich
89ee44d410 Add test for PCIe spread spectrum clocking 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-12-01 22:02:09 -08:00
Alex Forencich
36cf9c9b06 Remove unnecessary shadow valid registers 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-12-01 14:03:55 -08:00
Alex Forencich
be0d9b7b88 Improve handling of instance name mangling 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-12-01 13:37:25 -08:00
Alex Forencich
5560fa2b32 Fix timestamp capture/sync logic 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-30 14:05:16 -08:00
Alex Forencich
16cd84123d Add user_sma_clk pins to VCU108 and VCU118 constraints files 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-29 13:58:22 -08:00
Alex Forencich
bf3636ff15 fpga/mqnic: Add user_sma_clk pins to VCU108 and VCU118 constraints files 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-29 00:37:51 -08:00
Alex Forencich
ba55a3c1ed fpga/mqnic: Fix AXIL_CSR_ADDR_WIDTH parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-28 18:57:10 -08:00
Alex Forencich
a839ecf4cc fpga/mqnic/VCU118: Fix VCU118 refclk 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-28 00:20:31 -08:00
Alex Forencich
1f3b739bb6 fpga/mqnic: UltraScale devices use qpllrsvd pins for PCIe rate control 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-27 17:25:42 -08:00
Alex Forencich
51b9eb251b fpga/mqnic/ZCU106: Add notes for boot mode selection on ZCU106 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-23 00:51:38 -08:00
Alex Forencich
baf3279982 fpga/mqnic: Update transceiver wrappers to faciliate QPLL sharing 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-23 00:49:07 -08:00
Alex Forencich
d9c856b877 fpga/common: Update clock info register block timing constraints to handle clocks from OOC cores that are not defined during synthesis 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-23 00:41:21 -08:00
Alex Forencich
2e8e24f446 fpga/mqnic/Alveo: Fix Alveo flash format register 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-20 00:18:39 -08:00
Alex Forencich
179fd275b5 Update device lists 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-19 21:16:28 -08:00
Alex Forencich
c61bbd6f0d fpga/mqnic: Clean up IO constraints for Intel devices 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-19 21:15:05 -08:00
Alex Forencich
b4febeb78e fpga/mqnic: Add missing PTP clock connections 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-19 19:52:09 -08:00
Alex Forencich
98e76987e5 modules/mqnic: Set port phys_index 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-19 19:51:52 -08:00
Alex Forencich
e9ea91b5ec fpga/mqnic: Set data bus width correctly for 25G E-Tile MACs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-19 19:51:32 -08:00
Alex Forencich
a7753da72e Add support for BittWare IA-420F 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-19 19:51:12 -08:00
Alex Forencich
67e0e07c43 fpga/mqnic/DK_DEV_AGF014EA: set port group size based on selected MAC rate 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-19 19:50:29 -08:00
Alex Forencich
c48735216c fpga/mqnic/Alveo: Rework AU200 clocking 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-19 19:50:07 -08:00
Alex Forencich
534cd3735f fpga/mqnic/Alveo: Rework AU55 clocking 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-15 11:28:35 -08:00
Alex Forencich
cccd983975 fpga/mqnic/Alveo: Rework AU280 clocking 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-15 11:28:14 -08:00
Alex Forencich
152c96dc00 fpga/mqnic/Alveo: Rework AU50 clocking 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-15 11:25:45 -08:00
Alex Forencich
0c35085714 fpga/common/rtl: Update scheduler block parameters and PTP connections 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-14 21:51:15 -08:00
Alex Forencich
614b33a205 fpga/mqnic/DK_DEV_1SDX_P_A: Fix MAC timing constraints for DK-DEV-1SDX-P-A 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-14 18:19:29 -08:00
Alex Forencich
55c5ea335f fpga/mqnic/DK_DEV_AGF014EA: Fix MAC timing constraints for DK-DEV-AGF014EA 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-14 18:13:25 -08:00
Alex Forencich
184b7242e9 fpga/mqnic/DE10_Agilex: Fix MAC timing constraints for DE10-Agilex 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-14 18:11:59 -08:00
Alex Forencich
545fb3ca22 fpga/mqnic/XUPP3R: Add missing TCL script for XUSP3S PCIe IP core 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-14 17:54:03 -08:00
Alex Forencich
3f7a4cee27 fpga/mqnic: Fix datapath width parameter for 25G 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-13 21:39:42 -08:00
Alex Forencich
09af3eb882 fpga/mqnic/DK_DEV_1SDX_P_A: Mege 25G into 100G for DK-DEV-1SDX-P-A 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-13 21:38:20 -08:00
Alex Forencich
cbb2dda130 fpga/mqnic/DK_DEV_AGF014EA: Merge 25G into 100G for DK-DEV-AGF014EA 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-13 21:22:20 -08:00
Alex Forencich
0002f0476a fpga/mqnic/DE10_Agilex: Merge 25G into 100G for DE10-Agilex 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-13 20:49:04 -08:00
Alex Forencich
3b70f93722 fpga/mqnic: Rework parametrization for Intel 100G designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-13 19:16:32 -08:00
Alex Forencich
12cb29f9ee Update device lists 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-13 16:43:53 -08:00
Alex Forencich
23a142b237 fpga/mqnic/Alveo: Minor cleanup 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-13 16:38:13 -08:00
Alex Forencich
2d1e322738 modules/mqnic: Add board ID for AU45 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-13 14:36:09 -08:00
Alex Forencich
1330e59233 lib/mqnic: Add XCU26 to FPGA ID list 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-13 14:35:40 -08:00
Alex Forencich
4f60691485 fpga/mqnic/Alveo: Add parameters for flash config 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-13 12:39:20 -08:00
Alex Forencich
b2f853cae7 Warn if the application BAR didn't get enumerated 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-12 19:15:40 -08:00
Alex Forencich
45a6250e43 Update FPGA ID list and adjust part matching to handle multiple parts with the same JTAG ID 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-12 19:09:56 -08:00
Alex Forencich
2cebcdfb2a Add support for Alveo U55N/Varium C1100 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-12 18:30:05 -08:00
Alex Forencich
1707142ab1 fpga/mqnic/Alveo: Fix HBM debug hub configuration 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-12 11:43:28 -08:00
Alex Forencich
dddc84d9fa fpga/mqnic: Merge AU50 into unified Alveo design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-12 00:56:56 -08:00
Alex Forencich
38a8a2588b fpga/mqnic: Merge AU280 into unified Alveo design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-11 23:57:56 -08:00