Alex Forencich
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2a7d0e0947
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Use new PTP time distribution subsystem
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-11-07 21:57:07 -08:00 |
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Alex Forencich
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6b256f82d3
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Generate pause frames on TX
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-09-10 23:22:50 -07:00 |
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Alex Forencich
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9963674c61
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Add flow control
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-09-09 19:01:36 -07:00 |
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Alex Forencich
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bed12ee774
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Consolidate CQs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-07-10 17:52:34 -07:00 |
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Alex Forencich
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265035769a
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Reorganize queue control registers
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-07-07 01:19:19 -07:00 |
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Alex Forencich
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bb158d568f
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Add RX indirection table
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-04-10 15:05:32 -07:00 |
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Alex Forencich
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30379cd8a3
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Add phase tag to events and completions to avoid queue pointer reads
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-04-06 20:43:13 -07:00 |
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Alex Forencich
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b0fd1f3f3b
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Add documentation on RX queue map register block
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-02-01 18:50:08 -08:00 |
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Alex Forencich
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c396da2ebc
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Add documentation on clock info register block
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-02-01 18:49:52 -08:00 |
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Alex Forencich
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e4764bc600
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Add documentation on app info register block
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-02-01 18:49:32 -08:00 |
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Alex Forencich
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96bb163038
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Add documentation on port-level register blocks
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-02-01 18:49:15 -08:00 |
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Alex Forencich
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d3942da875
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fpga: Add clock info register block
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-10-15 19:45:02 -07:00 |
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Alex Forencich
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d7904b8007
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fpga: Add support for IRQ rate limiting
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-09-04 15:24:40 -07:00 |
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Alex Forencich
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c2fea3a616
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Add port register blocks with support for PHY link status reporting
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-05-04 09:03:37 -07:00 |
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Alex Forencich
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2bd8350276
|
Add RX queue mapping module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-04-23 00:12:22 -07:00 |
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Alex Forencich
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7f8bbe30de
|
Add application ID
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-04-21 13:15:45 -07:00 |
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Alex Forencich
|
eb530475fb
|
More expressive flash format register
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-04-15 18:38:01 -07:00 |
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Alex Forencich
|
1797fdecec
|
docs: Fix table
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-04-07 22:42:47 -07:00 |
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Alex Forencich
|
cbd9d0dfc6
|
Expose port and scheduler block counts in IF control block; update driver model, driver, and userspace tools to handle scheduler blocks separately from ports
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2022-03-28 17:23:27 -07:00 |
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Alex Forencich
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1e601cff56
|
Initial commit of sphinx documentation
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2022-03-13 23:32:01 -07:00 |
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