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3,255 Commits 1 Branch 0 Tags
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312 Commits

Author SHA1 Message Date
Alex Forencich
ba55a3c1ed fpga/mqnic: Fix AXIL_CSR_ADDR_WIDTH parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-28 18:57:10 -08:00
Alex Forencich
1f3b739bb6 fpga/mqnic: UltraScale devices use qpllrsvd pins for PCIe rate control 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-27 17:25:42 -08:00
Alex Forencich
baf3279982 fpga/mqnic: Update transceiver wrappers to faciliate QPLL sharing 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-23 00:49:07 -08:00
Alex Forencich
d9c856b877 fpga/common: Update clock info register block timing constraints to handle clocks from OOC cores that are not defined during synthesis 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-23 00:41:21 -08:00
Alex Forencich
0c35085714 fpga/common/rtl: Update scheduler block parameters and PTP connections 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-14 21:51:15 -08:00
Alex Forencich
495c29f263 Update to latest cocotbext-eth 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-10 19:21:05 -08:00
Alex Forencich
2a7d0e0947 Use new PTP time distribution subsystem 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-07 21:57:07 -08:00
Alex Forencich
d78700d3bf fpga: Remove redundant RX PTP clock 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-10-27 22:40:40 -07:00
Alex Forencich
6f2da7c1e9 fpga/common: Use async clocking for CMAC 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-10-27 22:40:08 -07:00
Alex Forencich
858dc5ac85 fpga/common: Fix address space layout 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-10-12 22:34:09 -07:00
Alex Forencich
d9e4b82f7a fpga: PTP sample clock is no longer optional, so remove PTP_USE_SAMPLE_CLOCK parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-24 13:52:06 -07:00
Alex Forencich
66b1a28159 Update ptp_clock_cdc instances 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-24 13:48:27 -07:00
Alex Forencich
6b256f82d3 Generate pause frames on TX 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-10 23:22:50 -07:00
Alex Forencich
9963674c61 Add flow control 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-09 19:01:36 -07:00
Alex Forencich
a169578cfd fpga/common/syn: Fix TDMA BER channel timing constraints 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-09 18:58:30 -07:00
Alex Forencich
36576d8981 Update MAC and PHY instances 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-28 17:22:34 -07:00
Alex Forencich
99645f894e Use shallow async FIFOs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-17 02:00:12 -07:00
Alex Forencich
7d2f77a30b fpga/common: Connect xcvr_ctrl_rst to QPLLs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-17 18:44:42 -07:00
Alex Forencich
a99815800b fpga/common: Fix GT wrapper timing constraints when DRP interface is tied off 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-17 18:43:07 -07:00
Alex Forencich
17443e9366 fpga/mqnic: Separate event and completion write instances 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-10 17:53:03 -07:00
Alex Forencich
bed12ee774 Consolidate CQs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-10 17:52:34 -07:00
Alex Forencich
265035769a Reorganize queue control registers 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-07 01:19:19 -07:00
Alex Forencich
448fa8eb4c Use SPDX 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-26 11:44:57 -07:00
Alex Forencich
edc5903157 fpga/common: Fix FIFO status connections 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-25 18:35:21 -07:00
Alex Forencich
b84b6b53cc fpga/common/tb: Fix testbench name 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-24 00:57:02 -07:00
Alex Forencich
a7e4c9e6eb fpga/common/tb: Fix testbench parameters in mqnic_core_axi testbench 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-24 00:56:47 -07:00
Alex Forencich
acfd88a043 fpga/common: Update Stratix 10 core logic based on RX completion buffer size test results 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-21 16:12:58 -07:00
Alex Forencich
f049e9bc37 fpga/common: Update US/US+ core logic based on RX completion buffer size test results 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-16 16:57:53 -07:00
Alex Forencich
45d941b63b fpga/common: Add I2C single reg module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-10 20:17:55 -07:00
Alex Forencich
64cdae1ccf fpga: Update designs for RX completion buffer management 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-31 10:26:40 -07:00
Alex Forencich
c45be17cea fpga/common: Add busy status outputs to DMA IF instances 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-30 21:27:56 -07:00
Alex Forencich
b7dad0e946 fpga/common/tb: Check feature bits in core testbenches 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-13 01:10:35 -07:00
Alex Forencich
1c242f7d92 fpga/common/tb: Pull out feature bits for easy access 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-13 00:54:56 -07:00
Alex Forencich
3c995dc8e0 Implement dynamic queue allocation in testbench and driver 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-02 21:23:30 -07:00
Alex Forencich
9834f8365c Rework resource management in testbenches, driver, and utils 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-01 22:04:43 -07:00
Alex Forencich
66f5b9fcc1 Clean up naming in testbenches, driver, and utils 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-30 21:48:34 -07:00
Alex Forencich
519330fd32 fpga: Move led_sreg_driver into common 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-27 14:12:42 -07:00
Alex Forencich
95af2136b1 fpga/common: Increase event FIFO size 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-14 01:03:19 -07:00
Alex Forencich
bb158d568f Add RX indirection table 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-10 15:05:32 -07:00
Alex Forencich
30379cd8a3 Add phase tag to events and completions to avoid queue pointer reads 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-06 20:43:13 -07:00
Alex Forencich
54b3c8199c fpga/common: Add re-arm bit in tail pointer register in completion queue manager 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-06 16:58:50 -07:00
Alex Forencich
04ede2e535 fpga/common: Update port timing constraints to not mark ASYNC_REG on the first flip flop in the status sync chains for better placement flexibility 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-06 14:34:22 -07:00
Alex Forencich
394dc2d723 fpga/common: Add phase bit to queue managers 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-05 01:38:46 -07:00
Alex Forencich
a8feaf2383 Advance TX/RX queue pointers based on completion records instead of MMIO reads 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-04 22:12:32 -07:00
Alex Forencich
d06fbaf178 fpga/common/tb: Rework driver model to better match C code 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-31 17:44:06 -07:00
Alex Forencich
ec1d7fe904 fpga/common/tb: Remove old interrupt handler 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-31 16:58:53 -07:00
Alex Forencich
223c6c020d fpga/common: Add DRAM/HBM to core testbenches 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-27 18:12:50 -07:00
Alex Forencich
b9945d3986 fpga/common: Pull out core_inst to simplify setup 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-26 23:18:55 -07:00
Alex Forencich
ca07a23afc fpga/common: Add extra non-ASYNC_REG registers on transceiver resets to permit replication 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-24 21:34:42 -08:00
Alex Forencich
0f86ea9bb1 fpga/common: Remove unnecessary reset from clock info register block 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-24 21:32:30 -08:00