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136 Commits

Author SHA1 Message Date
Alex Forencich
495c29f263 Update to latest cocotbext-eth 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-10 19:21:05 -08:00
Alex Forencich
2a7d0e0947 Use new PTP time distribution subsystem 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-07 21:57:07 -08:00
Alex Forencich
d9e4b82f7a fpga: PTP sample clock is no longer optional, so remove PTP_USE_SAMPLE_CLOCK parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-24 13:52:06 -07:00
Alex Forencich
6b256f82d3 Generate pause frames on TX 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-10 23:22:50 -07:00
Alex Forencich
9963674c61 Add flow control 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-09 19:01:36 -07:00
Alex Forencich
bed12ee774 Consolidate CQs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-10 17:52:34 -07:00
Alex Forencich
265035769a Reorganize queue control registers 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-07 01:19:19 -07:00
Alex Forencich
448fa8eb4c Use SPDX 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-26 11:44:57 -07:00
Alex Forencich
b84b6b53cc fpga/common/tb: Fix testbench name 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-24 00:57:02 -07:00
Alex Forencich
a7e4c9e6eb fpga/common/tb: Fix testbench parameters in mqnic_core_axi testbench 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-24 00:56:47 -07:00
Alex Forencich
64cdae1ccf fpga: Update designs for RX completion buffer management 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-31 10:26:40 -07:00
Alex Forencich
b7dad0e946 fpga/common/tb: Check feature bits in core testbenches 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-13 01:10:35 -07:00
Alex Forencich
1c242f7d92 fpga/common/tb: Pull out feature bits for easy access 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-13 00:54:56 -07:00
Alex Forencich
3c995dc8e0 Implement dynamic queue allocation in testbench and driver 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-02 21:23:30 -07:00
Alex Forencich
9834f8365c Rework resource management in testbenches, driver, and utils 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-01 22:04:43 -07:00
Alex Forencich
66f5b9fcc1 Clean up naming in testbenches, driver, and utils 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-30 21:48:34 -07:00
Alex Forencich
bb158d568f Add RX indirection table 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-10 15:05:32 -07:00
Alex Forencich
30379cd8a3 Add phase tag to events and completions to avoid queue pointer reads 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-06 20:43:13 -07:00
Alex Forencich
394dc2d723 fpga/common: Add phase bit to queue managers 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-05 01:38:46 -07:00
Alex Forencich
a8feaf2383 Advance TX/RX queue pointers based on completion records instead of MMIO reads 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-04 22:12:32 -07:00
Alex Forencich
d06fbaf178 fpga/common/tb: Rework driver model to better match C code 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-31 17:44:06 -07:00
Alex Forencich
ec1d7fe904 fpga/common/tb: Remove old interrupt handler 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-31 16:58:53 -07:00
Alex Forencich
223c6c020d fpga/common: Add DRAM/HBM to core testbenches 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-27 18:12:50 -07:00
Alex Forencich
b9945d3986 fpga/common: Pull out core_inst to simplify setup 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-26 23:18:55 -07:00
Alex Forencich
1682389fd0 Remove recursively-expanded macros for module parameters in makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-17 16:24:52 -08:00
Alex Forencich
e872c6c749 Rework parameter handling in testbench makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-29 23:20:44 -08:00
Alex Forencich
6c58e950d3 fpga/mqnic: Add DRAM interface module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-19 16:47:02 -08:00
Alex Forencich
e8aaadd102 fpga: Clean up top-level PCIe interface parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-04 23:56:56 -08:00
Alex Forencich
6d4373ec97 fpga/common: Rework stats counter to use pipeline and infer URAM 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-01 17:15:56 -08:00
Alex Forencich
d3942da875 fpga: Add clock info register block 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-15 19:45:02 -07:00
Alex Forencich
d0cc106783 fpga: Remove redundant RX_RSS_ENABLE parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-13 17:10:25 -07:00
Alex Forencich
ebbddb5559 fpga/common: Add multiple queue test to core testbenches 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-20 21:59:02 -07:00
Alex Forencich
d7904b8007 fpga: Add support for IRQ rate limiting 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-04 15:24:40 -07:00
Alex Forencich
1486da601f fpga: Add clock period parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-04 12:03:35 -07:00
Alex Forencich
81648cf85b fpga/mqnic: Clean up PCIe DMA IF flow control connections 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-03 23:04:05 -07:00
Alex Forencich
3f57c2143b fpga/mqnic: PCIe interface updates 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-03 12:28:49 -07:00
Alex Forencich
4b6a96d5ee Add mqnic core logic for Intel P-Tile 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 23:15:54 -07:00
Alex Forencich
e0d92172d3 Separate PTP TX clock input 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:24:41 -07:00
Alex Forencich
33b798540e Change hex format in makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-09 14:20:48 -07:00
Alex Forencich
729c3a0458 Update for PCIe shim changes, enable TLP straddling on US/US+ devices, and use 256 tags on US+ devices 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-08 22:07:18 -07:00
Alex Forencich
a5d7833bd9 Update testbenches for new version of cocotbext-pcie 2022-06-05 00:24:42 -07:00
Alex Forencich
21b0f014a5 Switch to MSI-X 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-02 23:58:29 -07:00
Alex Forencich
dd2853bf40 Update testbenches for latest version of cocotbext-pcie 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-30 13:10:39 -07:00
Alex Forencich
835f0d38f0 Update PTP subsystem to use separate clock for improved stability 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-06 17:46:16 -07:00
Alex Forencich
c2fea3a616 Add port register blocks with support for PHY link status reporting 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-04 09:03:37 -07:00
Alex Forencich
cfdd6f5455 Decouple transmit completion handling from PTP timestamping 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-01 17:41:47 -07:00
Alex Forencich
53f3547ef5 Rework hierarchy to move port-specific logic out of mqnic_core and into mqnic_interface and new port-level modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-29 14:32:57 -07:00
Alex Forencich
d5c2566dff Add statistics collection for AXI DMA IF 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-23 13:12:50 -07:00
Alex Forencich
2bd8350276 Add RX queue mapping module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-23 00:12:22 -07:00
Alex Forencich
28bbae908b fpga/common: Store receive queue index in packet object in driver model 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-22 19:04:26 -07:00