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3,255 Commits 1 Branch 0 Tags
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539 Commits

Author SHA1 Message Date
Alex Forencich
bf3636ff15 fpga/mqnic: Add user_sma_clk pins to VCU108 and VCU118 constraints files 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-29 00:37:51 -08:00
Alex Forencich
ba55a3c1ed fpga/mqnic: Fix AXIL_CSR_ADDR_WIDTH parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-28 18:57:10 -08:00
Alex Forencich
a839ecf4cc fpga/mqnic/VCU118: Fix VCU118 refclk 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-28 00:20:31 -08:00
Alex Forencich
1f3b739bb6 fpga/mqnic: UltraScale devices use qpllrsvd pins for PCIe rate control 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-27 17:25:42 -08:00
Alex Forencich
51b9eb251b fpga/mqnic/ZCU106: Add notes for boot mode selection on ZCU106 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-23 00:51:38 -08:00
Alex Forencich
baf3279982 fpga/mqnic: Update transceiver wrappers to faciliate QPLL sharing 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-23 00:49:07 -08:00
Alex Forencich
2e8e24f446 fpga/mqnic/Alveo: Fix Alveo flash format register 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-20 00:18:39 -08:00
Alex Forencich
c61bbd6f0d fpga/mqnic: Clean up IO constraints for Intel devices 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-19 21:15:05 -08:00
Alex Forencich
b4febeb78e fpga/mqnic: Add missing PTP clock connections 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-19 19:52:09 -08:00
Alex Forencich
e9ea91b5ec fpga/mqnic: Set data bus width correctly for 25G E-Tile MACs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-19 19:51:32 -08:00
Alex Forencich
a7753da72e Add support for BittWare IA-420F 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-19 19:51:12 -08:00
Alex Forencich
67e0e07c43 fpga/mqnic/DK_DEV_AGF014EA: set port group size based on selected MAC rate 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-19 19:50:29 -08:00
Alex Forencich
c48735216c fpga/mqnic/Alveo: Rework AU200 clocking 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-19 19:50:07 -08:00
Alex Forencich
534cd3735f fpga/mqnic/Alveo: Rework AU55 clocking 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-15 11:28:35 -08:00
Alex Forencich
cccd983975 fpga/mqnic/Alveo: Rework AU280 clocking 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-15 11:28:14 -08:00
Alex Forencich
152c96dc00 fpga/mqnic/Alveo: Rework AU50 clocking 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-15 11:25:45 -08:00
Alex Forencich
614b33a205 fpga/mqnic/DK_DEV_1SDX_P_A: Fix MAC timing constraints for DK-DEV-1SDX-P-A 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-14 18:19:29 -08:00
Alex Forencich
55c5ea335f fpga/mqnic/DK_DEV_AGF014EA: Fix MAC timing constraints for DK-DEV-AGF014EA 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-14 18:13:25 -08:00
Alex Forencich
184b7242e9 fpga/mqnic/DE10_Agilex: Fix MAC timing constraints for DE10-Agilex 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-14 18:11:59 -08:00
Alex Forencich
545fb3ca22 fpga/mqnic/XUPP3R: Add missing TCL script for XUSP3S PCIe IP core 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-14 17:54:03 -08:00
Alex Forencich
3f7a4cee27 fpga/mqnic: Fix datapath width parameter for 25G 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-13 21:39:42 -08:00
Alex Forencich
09af3eb882 fpga/mqnic/DK_DEV_1SDX_P_A: Mege 25G into 100G for DK-DEV-1SDX-P-A 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-13 21:38:20 -08:00
Alex Forencich
cbb2dda130 fpga/mqnic/DK_DEV_AGF014EA: Merge 25G into 100G for DK-DEV-AGF014EA 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-13 21:22:20 -08:00
Alex Forencich
0002f0476a fpga/mqnic/DE10_Agilex: Merge 25G into 100G for DE10-Agilex 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-13 20:49:04 -08:00
Alex Forencich
3b70f93722 fpga/mqnic: Rework parametrization for Intel 100G designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-13 19:16:32 -08:00
Alex Forencich
23a142b237 fpga/mqnic/Alveo: Minor cleanup 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-13 16:38:13 -08:00
Alex Forencich
4f60691485 fpga/mqnic/Alveo: Add parameters for flash config 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-13 12:39:20 -08:00
Alex Forencich
2cebcdfb2a Add support for Alveo U55N/Varium C1100 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-12 18:30:05 -08:00
Alex Forencich
1707142ab1 fpga/mqnic/Alveo: Fix HBM debug hub configuration 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-12 11:43:28 -08:00
Alex Forencich
dddc84d9fa fpga/mqnic: Merge AU50 into unified Alveo design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-12 00:56:56 -08:00
Alex Forencich
38a8a2588b fpga/mqnic: Merge AU280 into unified Alveo design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-11 23:57:56 -08:00
Alex Forencich
b8ef9cc92b fpga/mqnic/Alveo: Add HBM interfaces 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-11 16:34:17 -08:00
Alex Forencich
d3064877ea fpga/mqnic/Alveo: Rework Alveo parametrization 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-11 13:39:33 -08:00
Alex Forencich
7914445ac0 Rename AU200 to Alveo 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-07 22:48:37 -08:00
Alex Forencich
cd7ec5d5e3 fpga/mqnic Merge BittWare XUP-P3R and XUSP3S designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-07 22:27:54 -08:00
Alex Forencich
bd6ffeab99 fpga/mqnic: Merge Cisco Nexus K35-S and K3P-S designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-07 22:01:03 -08:00
Alex Forencich
2a7d0e0947 Use new PTP time distribution subsystem 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-07 21:57:07 -08:00
Alex Forencich
d78700d3bf fpga: Remove redundant RX PTP clock 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-10-27 22:40:40 -07:00
Alex Forencich
18ac7cc4f4 fpga/mqnic: Merge AU200, AU250, and VCU1525 designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-10-12 23:26:08 -07:00
Alex Forencich
d9e4b82f7a fpga: PTP sample clock is no longer optional, so remove PTP_USE_SAMPLE_CLOCK parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-24 13:52:06 -07:00
Alex Forencich
70ff3e9383 fpga/mqnic: Enable devlink and DSA on petalinux 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-14 19:17:02 -07:00
Alex Forencich
5e53dd10ea fpga/mqnic: Increase RX FIFO size 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-11 22:47:35 -07:00
Alex Forencich
9963674c61 Add flow control 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-09 19:01:36 -07:00
Alex Forencich
6e260f3e79 fpga/mqnic: Update modified FIFO modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-07 20:10:48 -07:00
Alex Forencich
57ffccba15 fpga/mqnic: Cleanup 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-07 18:50:55 -07:00
Alex Forencich
719231b878 fpga/mqnic/VCU118: Update VCU118 makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-07 18:41:15 -07:00
Alex Forencich
e0b31d9b94 fpga/mqnic: Add MAC-related parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-07 18:35:42 -07:00
Alex Forencich
31ced63c91 fpga/mqnic: Add missing XGMII parameter connections 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-07 18:30:13 -07:00
Alex Forencich
2e387d3630 fpga/mqnic: Ensure class code lookup assistant is disabled in PCIe core instances 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-05 23:44:12 -07:00
Alex Forencich
06226ac777 fpga/mqnic: Fix PCIe subsystem vendor IDs on UltraScale devices 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-04 23:05:25 -07:00