FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-16 08:12:53 +08:00
Code Issues Projects Releases Wiki Activity
3,255 Commits 1 Branch 0 Tags
Commit Graph

56 Commits

Author SHA1 Message Date
Alex Forencich
ba55a3c1ed fpga/mqnic: Fix AXIL_CSR_ADDR_WIDTH parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-28 18:57:10 -08:00
Alex Forencich
1f3b739bb6 fpga/mqnic: UltraScale devices use qpllrsvd pins for PCIe rate control 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-27 17:25:42 -08:00
Alex Forencich
baf3279982 fpga/mqnic: Update transceiver wrappers to faciliate QPLL sharing 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-23 00:49:07 -08:00
Alex Forencich
2a7d0e0947 Use new PTP time distribution subsystem 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-07 21:57:07 -08:00
Alex Forencich
d78700d3bf fpga: Remove redundant RX PTP clock 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-10-27 22:40:40 -07:00
Alex Forencich
d9e4b82f7a fpga: PTP sample clock is no longer optional, so remove PTP_USE_SAMPLE_CLOCK parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-24 13:52:06 -07:00
Alex Forencich
5e53dd10ea fpga/mqnic: Increase RX FIFO size 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-11 22:47:35 -07:00
Alex Forencich
9963674c61 Add flow control 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-09 19:01:36 -07:00
Alex Forencich
57ffccba15 fpga/mqnic: Cleanup 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-07 18:50:55 -07:00
Alex Forencich
e0b31d9b94 fpga/mqnic: Add MAC-related parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-07 18:35:42 -07:00
Alex Forencich
31ced63c91 fpga/mqnic: Add missing XGMII parameter connections 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-07 18:30:13 -07:00
Alex Forencich
2e387d3630 fpga/mqnic: Ensure class code lookup assistant is disabled in PCIe core instances 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-05 23:44:12 -07:00
Alex Forencich
7e497db017 fpga/mqnic: Clean up PCIe core instances 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-04 23:04:58 -07:00
Alex Forencich
36576d8981 Update MAC and PHY instances 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-28 17:22:34 -07:00
Alex Forencich
c5af0f726a fpga/mqnic: Use arrays for QSFP pins 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-28 12:21:09 -07:00
Alex Forencich
a052b0eb32 Procedural generation of testbench drivers 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-28 18:38:12 -07:00
Alex Forencich
ed4a26e2cb Update Vivado makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 18:45:01 -07:00
Alex Forencich
bed12ee774 Consolidate CQs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-10 17:52:34 -07:00
Alex Forencich
448fa8eb4c Use SPDX 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-26 11:44:57 -07:00
Alex Forencich
9a93cfb5ad fpga/mqnic: Clean up readmes 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-26 00:08:49 -07:00
Alex Forencich
64cdae1ccf fpga: Update designs for RX completion buffer management 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-31 10:26:40 -07:00
Alex Forencich
9834f8365c Rework resource management in testbenches, driver, and utils 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-01 22:04:43 -07:00
Alex Forencich
66f5b9fcc1 Clean up naming in testbenches, driver, and utils 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-30 21:48:34 -07:00
Alex Forencich
bb158d568f Add RX indirection table 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-10 15:05:32 -07:00
Alex Forencich
c273b7f4ad mqnic: Register MIG resets 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-05 17:06:57 -07:00
Alex Forencich
3d06b34679 fpga: Add DRAM bandwidth test to DMA benchmark application 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-29 14:27:46 -07:00
Alex Forencich
554369b33b fpga/mqnic: Update makefile path handling 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-24 00:39:45 -07:00
Alex Forencich
1682389fd0 Remove recursively-expanded macros for module parameters in makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-17 16:24:52 -08:00
Alex Forencich
e872c6c749 Rework parameter handling in testbench makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-29 23:20:44 -08:00
Alex Forencich
6c58e950d3 fpga/mqnic: Add DRAM interface module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-19 16:47:02 -08:00
Alex Forencich
aee97e4825 fpga/mqnic: Add performance-related MIG settings to config.tcl 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-17 23:16:19 -08:00
Alex Forencich
76553e3bba fpga/mqnic/250_SoC: Add DMA bench target for BittWare 250-SoC 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:10:53 -08:00
Alex Forencich
e8aaadd102 fpga: Clean up top-level PCIe interface parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-04 23:56:56 -08:00
Alex Forencich
08f49d7e17 fpga/mqnic: Add missing DRP frequency parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-04 22:07:58 -08:00
Alex Forencich
0644a12a48 fpga/mqnic: Remove extraneous top-level parameter RX_RSS_ENABLE from config.tcl scripts 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-03 21:32:51 -08:00
Alex Forencich
347a03b347 fpga/mqnic: Rework PCIe IP core configuration, fixes disrupted MSI-X settings with application section enabled and issues with PCIe class code on 7-series and UltraScale 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-03 18:16:12 -08:00
Alex Forencich
c5003d0c6d fpga/mqnic: Select advanced mode for Xilinx PCIe IP core config to access MSI-X settings 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-03 15:35:16 -08:00
Alex Forencich
db621ffa7d Use CMAC wrapper in 100G mqnic design for 250-SoC 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-10 18:01:43 -08:00
Alex Forencich
d3942da875 fpga: Add clock info register block 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-15 19:45:02 -07:00
Alex Forencich
d0cc106783 fpga: Remove redundant RX_RSS_ENABLE parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-13 17:10:25 -07:00
Alex Forencich
01df80df86 fpga/mqnic: Disable MIGs by default 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-12 23:57:27 -07:00
Alex Forencich
5e52a52f5e fpga/mqnic: Add MIGs and HBM controllers for most boards 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-12 19:00:49 -07:00
Alex Forencich
eb990643f2 fpga/mqnic: various minor cleanup 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-12 17:12:07 -07:00
Alex Forencich
5f1e74b0e1 Add PROJECT variable, remove multiple stem matches 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-11 13:33:09 -07:00
Alex Forencich
7017e7d49b Explicitly set top module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-11 12:29:01 -07:00
Alex Forencich
ceb6a9ca06 Update clean target 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-11 12:26:39 -07:00
Alex Forencich
9c98f12392 Write debug probes file alongside bit file 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-10 23:37:54 -07:00
Alex Forencich
9628401780 Normalize output file location 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-10 21:47:53 -07:00
Alex Forencich
caf2a0993b fpga: Output hierarchical utilization reports 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-06 21:17:25 -07:00
Alex Forencich
d7904b8007 fpga: Add support for IRQ rate limiting 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-04 15:24:40 -07:00