Alex Forencich
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ba55a3c1ed
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fpga/mqnic: Fix AXIL_CSR_ADDR_WIDTH parameter
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-11-28 18:57:10 -08:00 |
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Alex Forencich
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2a7d0e0947
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Use new PTP time distribution subsystem
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-11-07 21:57:07 -08:00 |
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Alex Forencich
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d9e4b82f7a
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fpga: PTP sample clock is no longer optional, so remove PTP_USE_SAMPLE_CLOCK parameter
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-09-24 13:52:06 -07:00 |
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Alex Forencich
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5e53dd10ea
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fpga/mqnic: Increase RX FIFO size
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-09-11 22:47:35 -07:00 |
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Alex Forencich
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9963674c61
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Add flow control
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-09-09 19:01:36 -07:00 |
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Alex Forencich
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6e260f3e79
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fpga/mqnic: Update modified FIFO modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-09-07 20:10:48 -07:00 |
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Alex Forencich
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e0b31d9b94
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fpga/mqnic: Add MAC-related parameters
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-09-07 18:35:42 -07:00 |
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Alex Forencich
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36576d8981
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Update MAC and PHY instances
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-08-28 17:22:34 -07:00 |
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Alex Forencich
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a052b0eb32
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Procedural generation of testbench drivers
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-07-28 18:38:12 -07:00 |
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Alex Forencich
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bed12ee774
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Consolidate CQs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-07-10 17:52:34 -07:00 |
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Alex Forencich
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448fa8eb4c
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Use SPDX
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-06-26 11:44:57 -07:00 |
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Alex Forencich
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9a93cfb5ad
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fpga/mqnic: Clean up readmes
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-06-26 00:08:49 -07:00 |
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Alex Forencich
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2c8b1d0e29
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fpga/mqnic/520N_MX: Add 25G mqnic design for BittWare 520N-MX
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-06-12 15:36:26 -07:00 |
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