Alex Forencich
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ba55a3c1ed
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fpga/mqnic: Fix AXIL_CSR_ADDR_WIDTH parameter
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-11-28 18:57:10 -08:00 |
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Alex Forencich
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1f3b739bb6
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fpga/mqnic: UltraScale devices use qpllrsvd pins for PCIe rate control
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-11-27 17:25:42 -08:00 |
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Alex Forencich
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baf3279982
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fpga/mqnic: Update transceiver wrappers to faciliate QPLL sharing
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-11-23 00:49:07 -08:00 |
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Alex Forencich
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2e8e24f446
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fpga/mqnic/Alveo: Fix Alveo flash format register
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-11-20 00:18:39 -08:00 |
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Alex Forencich
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c48735216c
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fpga/mqnic/Alveo: Rework AU200 clocking
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-11-19 19:50:07 -08:00 |
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Alex Forencich
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534cd3735f
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fpga/mqnic/Alveo: Rework AU55 clocking
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-11-15 11:28:35 -08:00 |
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Alex Forencich
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cccd983975
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fpga/mqnic/Alveo: Rework AU280 clocking
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-11-15 11:28:14 -08:00 |
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Alex Forencich
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152c96dc00
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fpga/mqnic/Alveo: Rework AU50 clocking
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-11-15 11:25:45 -08:00 |
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Alex Forencich
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23a142b237
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fpga/mqnic/Alveo: Minor cleanup
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-11-13 16:38:13 -08:00 |
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Alex Forencich
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4f60691485
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fpga/mqnic/Alveo: Add parameters for flash config
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-11-13 12:39:20 -08:00 |
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Alex Forencich
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2cebcdfb2a
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Add support for Alveo U55N/Varium C1100
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-11-12 18:30:05 -08:00 |
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Alex Forencich
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1707142ab1
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fpga/mqnic/Alveo: Fix HBM debug hub configuration
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-11-12 11:43:28 -08:00 |
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Alex Forencich
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dddc84d9fa
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fpga/mqnic: Merge AU50 into unified Alveo design
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-11-12 00:56:56 -08:00 |
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Alex Forencich
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38a8a2588b
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fpga/mqnic: Merge AU280 into unified Alveo design
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-11-11 23:57:56 -08:00 |
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Alex Forencich
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b8ef9cc92b
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fpga/mqnic/Alveo: Add HBM interfaces
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-11-11 16:34:17 -08:00 |
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Alex Forencich
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d3064877ea
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fpga/mqnic/Alveo: Rework Alveo parametrization
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-11-11 13:39:33 -08:00 |
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Alex Forencich
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7914445ac0
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Rename AU200 to Alveo
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-11-07 22:48:37 -08:00 |
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