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3,255 Commits 1 Branch 0 Tags
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44 Commits

Author SHA1 Message Date
Alex Forencich
ba55a3c1ed fpga/mqnic: Fix AXIL_CSR_ADDR_WIDTH parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-28 18:57:10 -08:00
Alex Forencich
c61bbd6f0d fpga/mqnic: Clean up IO constraints for Intel devices 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-19 21:15:05 -08:00
Alex Forencich
e9ea91b5ec fpga/mqnic: Set data bus width correctly for 25G E-Tile MACs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-19 19:51:32 -08:00
Alex Forencich
184b7242e9 fpga/mqnic/DE10_Agilex: Fix MAC timing constraints for DE10-Agilex 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-14 18:11:59 -08:00
Alex Forencich
3f7a4cee27 fpga/mqnic: Fix datapath width parameter for 25G 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-13 21:39:42 -08:00
Alex Forencich
0002f0476a fpga/mqnic/DE10_Agilex: Merge 25G into 100G for DE10-Agilex 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-13 20:49:04 -08:00
Alex Forencich
3b70f93722 fpga/mqnic: Rework parametrization for Intel 100G designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-13 19:16:32 -08:00
Alex Forencich
2a7d0e0947 Use new PTP time distribution subsystem 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-07 21:57:07 -08:00
Alex Forencich
d9e4b82f7a fpga: PTP sample clock is no longer optional, so remove PTP_USE_SAMPLE_CLOCK parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-24 13:52:06 -07:00
Alex Forencich
9963674c61 Add flow control 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-09 19:01:36 -07:00
Alex Forencich
6e260f3e79 fpga/mqnic: Update modified FIFO modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-07 20:10:48 -07:00
Alex Forencich
a052b0eb32 Procedural generation of testbench drivers 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-28 18:38:12 -07:00
Alex Forencich
bed12ee774 Consolidate CQs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-10 17:52:34 -07:00
Alex Forencich
448fa8eb4c Use SPDX 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-26 11:44:57 -07:00
Alex Forencich
9a93cfb5ad fpga/mqnic: Clean up readmes 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-26 00:08:49 -07:00
Alex Forencich
344fcd45fc fpga/mqnic: Testbench parameter clean-up 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-24 01:25:25 -07:00
Alex Forencich
5638287413 fpga/mqnic: Fix P-tile parameter names 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-07 11:09:33 -07:00
Alex Forencich
9834f8365c Rework resource management in testbenches, driver, and utils 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-01 22:04:43 -07:00
Alex Forencich
66f5b9fcc1 Clean up naming in testbenches, driver, and utils 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-30 21:48:34 -07:00
Alex Forencich
f4c016a46c fpga/mqnic/DE10-Agilex: Drop part suffix for production parts 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-15 16:56:10 -07:00
Alex Forencich
14be62110e fpga/mqnic: Write compressed SOF files 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-15 16:29:37 -07:00
Alex Forencich
adeb6d7a11 fpga/mqnic/DE10_Agilex: Report correct FPGA IDs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-15 16:26:39 -07:00
Alex Forencich
a3319d50b6 fpga/mqnic: Implement workaround for Quartus MLAB RAM read enable bug 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-14 01:21:36 -07:00
Alex Forencich
bb158d568f Add RX indirection table 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-10 15:05:32 -07:00
Alex Forencich
f54fe4100a fpga/mqnic: Update Intel IP TCL files for E-Tile 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-30 13:50:59 -07:00
Alex Forencich
554369b33b fpga/mqnic: Update makefile path handling 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-24 00:39:45 -07:00
Alex Forencich
1682389fd0 Remove recursively-expanded macros for module parameters in makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-17 16:24:52 -08:00
Alex Forencich
e872c6c749 Rework parameter handling in testbench makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-29 23:20:44 -08:00
Alex Forencich
e7dc033c78 fpga/mqnic/DE10_Agilex: Add DMA bench target for Terasic DE10-Agilex 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:18:40 -08:00
Alex Forencich
4b7d51133f fpga/mqnic: Enable statistics counters on all targets 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 13:06:39 -08:00
Alex Forencich
e8aaadd102 fpga: Clean up top-level PCIe interface parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-04 23:56:56 -08:00
Alex Forencich
0644a12a48 fpga/mqnic: Remove extraneous top-level parameter RX_RSS_ENABLE from config.tcl scripts 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-03 21:32:51 -08:00
Alex Forencich
d3942da875 fpga: Add clock info register block 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-15 19:45:02 -07:00
Alex Forencich
d0cc106783 fpga: Remove redundant RX_RSS_ENABLE parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-13 17:10:25 -07:00
Alex Forencich
5e52a52f5e fpga/mqnic: Add MIGs and HBM controllers for most boards 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-12 19:00:49 -07:00
Alex Forencich
eb990643f2 fpga/mqnic: various minor cleanup 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-12 17:12:07 -07:00
Alex Forencich
d7904b8007 fpga: Add support for IRQ rate limiting 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-04 15:24:40 -07:00
Alex Forencich
1486da601f fpga: Add clock period parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-04 12:03:35 -07:00
Alex Forencich
6c6648f114 fpga/mqnic: Add RAM inference directive to Intel designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-05 16:27:29 -07:00
Alex Forencich
81648cf85b fpga/mqnic: Clean up PCIe DMA IF flow control connections 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-03 23:04:05 -07:00
Alex Forencich
3f57c2143b fpga/mqnic: PCIe interface updates 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-03 12:28:49 -07:00
Alex Forencich
607ce498cf fpga/mqnic: Update PCIe DMA settings on Intel designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-03 00:42:19 -07:00
Alex Forencich
4bcac62c2a fpga/mqnic: Disable PTP on 100G E-tile designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-03 00:41:53 -07:00
Alex Forencich
ec17500a66 Add 100G mqnic design for DE10-Agilex 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-21 18:49:35 -07:00