Alex Forencich
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1f3b739bb6
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fpga/mqnic: UltraScale devices use qpllrsvd pins for PCIe rate control
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-11-27 17:25:42 -08:00 |
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Alex Forencich
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baf3279982
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fpga/mqnic: Update transceiver wrappers to faciliate QPLL sharing
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-11-23 00:49:07 -08:00 |
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Alex Forencich
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2e387d3630
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fpga/mqnic: Ensure class code lookup assistant is disabled in PCIe core instances
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-09-05 23:44:12 -07:00 |
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Alex Forencich
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448fa8eb4c
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Use SPDX
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-06-26 11:44:57 -07:00 |
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Alex Forencich
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c5003d0c6d
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fpga/mqnic: Select advanced mode for Xilinx PCIe IP core config to access MSI-X settings
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-12-03 15:35:16 -08:00 |
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Alex Forencich
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ad18c19da9
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fpga/mqnic: Fix default class code for UltraScale and 7-series devices
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-12-03 15:33:52 -08:00 |
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Alex Forencich
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5e52a52f5e
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fpga/mqnic: Add MIGs and HBM controllers for most boards
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-10-12 19:00:49 -07:00 |
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Alex Forencich
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0afe9be906
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fpga/mqnic/VCU108: Update VCU108 design to support 25G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-07-26 23:26:11 -07:00 |
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