Alex Forencich
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1f3b739bb6
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fpga/mqnic: UltraScale devices use qpllrsvd pins for PCIe rate control
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-11-27 17:25:42 -08:00 |
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Alex Forencich
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baf3279982
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fpga/mqnic: Update transceiver wrappers to faciliate QPLL sharing
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-11-23 00:49:07 -08:00 |
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Alex Forencich
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448fa8eb4c
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Use SPDX
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-06-26 11:44:57 -07:00 |
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Alex Forencich
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5e52a52f5e
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fpga/mqnic: Add MIGs and HBM controllers for most boards
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-10-12 19:00:49 -07:00 |
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Alex Forencich
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647a168299
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Enable more peripherals in Zynq designs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-08-16 18:49:02 -07:00 |
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Alex Forencich
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57905a5ef9
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fpga/mqnic/ZCU106/fpga_zynqmp: Rewrite zynq PS TCL script, rework PS clock settings, switch to 300 MHz PL clock
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-04-11 12:25:51 -07:00 |
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Andreas Braun
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dc77c9e92a
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ZCU106/fpga_zynqmp: Reduce number of IRQs to number of CPU cores
Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
Signed-off-by: Andreas Braun <andreas.braun@missinglinkelectronics.com>
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2022-03-31 17:22:27 +02:00 |
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Andreas Braun
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35517037e6
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ZCU106/: Add design based on ZynqMP PS as host system, Vivado v2021.1
Signed-off-by: Andreas Braun <andreas.braun@missinglinkelectronics.com>
Signed-off-by: Joachim Förster <joachim.foerster@missinglinkelectronics.com>
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2022-03-31 17:22:27 +02:00 |
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