Alex Forencich
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ba55a3c1ed
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fpga/mqnic: Fix AXIL_CSR_ADDR_WIDTH parameter
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-11-28 18:57:10 -08:00 |
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Alex Forencich
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1f3b739bb6
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fpga/mqnic: UltraScale devices use qpllrsvd pins for PCIe rate control
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-11-27 17:25:42 -08:00 |
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Alex Forencich
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baf3279982
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fpga/mqnic: Update transceiver wrappers to faciliate QPLL sharing
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-11-23 00:49:07 -08:00 |
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Alex Forencich
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2a7d0e0947
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Use new PTP time distribution subsystem
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-11-07 21:57:07 -08:00 |
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Alex Forencich
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d78700d3bf
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fpga: Remove redundant RX PTP clock
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-10-27 22:40:40 -07:00 |
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Alex Forencich
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d9e4b82f7a
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fpga: PTP sample clock is no longer optional, so remove PTP_USE_SAMPLE_CLOCK parameter
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-09-24 13:52:06 -07:00 |
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Alex Forencich
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5e53dd10ea
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fpga/mqnic: Increase RX FIFO size
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-09-11 22:47:35 -07:00 |
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Alex Forencich
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9963674c61
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Add flow control
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-09-09 19:01:36 -07:00 |
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Alex Forencich
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e0b31d9b94
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fpga/mqnic: Add MAC-related parameters
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-09-07 18:35:42 -07:00 |
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Alex Forencich
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2e387d3630
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fpga/mqnic: Ensure class code lookup assistant is disabled in PCIe core instances
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-09-05 23:44:12 -07:00 |
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Alex Forencich
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36576d8981
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Update MAC and PHY instances
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-08-28 17:22:34 -07:00 |
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Alex Forencich
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c5af0f726a
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fpga/mqnic: Use arrays for QSFP pins
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-08-28 12:21:09 -07:00 |
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Alex Forencich
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6e67bd652e
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fpga/mqnic/fb4CGg3: Add DRAM support on fb4CGg3
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-08-22 23:53:13 -07:00 |
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Alex Forencich
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a052b0eb32
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Procedural generation of testbench drivers
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-07-28 18:38:12 -07:00 |
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Alex Forencich
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ed4a26e2cb
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Update Vivado makefiles
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-07-13 18:45:01 -07:00 |
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Alex Forencich
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bed12ee774
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Consolidate CQs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-07-10 17:52:34 -07:00 |
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Alex Forencich
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448fa8eb4c
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Use SPDX
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-06-26 11:44:57 -07:00 |
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Alex Forencich
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9a93cfb5ad
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fpga/mqnic: Clean up readmes
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-06-26 00:08:49 -07:00 |
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Alex Forencich
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64cdae1ccf
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fpga: Update designs for RX completion buffer management
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-05-31 10:26:40 -07:00 |
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Alex Forencich
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9834f8365c
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Rework resource management in testbenches, driver, and utils
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-05-01 22:04:43 -07:00 |
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Alex Forencich
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66f5b9fcc1
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Clean up naming in testbenches, driver, and utils
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-04-30 21:48:34 -07:00 |
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Alex Forencich
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53d272ff12
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fpga/mqnic/fb4CGg3: Add 25G mqnic design for Silicom fb4CGg3@VU09P
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-04-30 13:55:58 -07:00 |
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Alex Forencich
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341115d70b
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fpga/mqnic/fb4CGg3: Add 100G mqnic design for Silicom fb4CGg3@VU09P
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-04-30 13:51:57 -07:00 |
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