925 Commits

Author	SHA1	Message	Date
Alex Forencich	6229e73044	Add missing i2c connections	2020-09-25 16:40:31 -07:00
Alex Forencich	94c2861de7	Use correct init_clk frequency	2020-09-23 14:25:48 -07:00
Alex Forencich	15022b3d94	Add 100G mqnic design for fb2CG@KU15P	2020-09-22 23:11:25 -07:00
Alex Forencich	1cd406f56f	Add 10G mqnic design for fb2CG@KU15P	2020-09-22 23:10:53 -07:00
Alex Forencich	72afcc44fe	Add 100G mqnic design for Alveo U250	2020-09-22 01:01:23 -07:00
Alex Forencich	5ddff9d17e	Add 100G mqnic design for Alveo U200	2020-09-22 01:01:07 -07:00
Alex Forencich	cbd7dbdbd5	Add 10G mqnic design for Alveo U250	2020-09-22 01:00:42 -07:00
Alex Forencich	6f72ac05b7	Add 10G mqnic design for Alveo U200	2020-09-22 01:00:23 -07:00
Alex Forencich	70b7082fb6	Implement new control registers	2020-09-19 17:25:58 -07:00
Alex Forencich	a37d9b3465	New transceiver control reigster definitions	2020-09-19 17:25:58 -07:00
Alex Forencich	3284ec3848	New I2C register definitions	2020-09-19 17:25:58 -07:00
Alex Forencich	f5f9cdca8b	merged changes in eth	2020-09-09 23:37:46 -07:00
Alex Forencich	cbaffeeac7	Limit RX DMA size to configured MTU size	2020-08-25 18:48:17 -07:00
Alex Forencich	f8dca522a1	Add missing symlink	2020-08-20 12:26:24 -07:00
Alex Forencich	c8f5bb235c	Remove extraneous clock connections	2020-08-19 18:33:41 -07:00
Alex Forencich	171eb144cb	Update U280 placement constraints	2020-08-17 18:37:31 -07:00
Alex Forencich	bb19674dac	merged changes in pcie	2020-08-17 18:34:37 -07:00
Alex Forencich	44dd74eb0d	merged changes in eth	2020-08-17 18:33:49 -07:00
Alex Forencich	6b9a6c87d5	merged changes in axi	2020-08-17 18:33:45 -07:00
Alex Forencich	e6b35f0567	Add PCIe mqnic design for ZCU106	2020-08-06 23:25:23 -07:00
Alex Forencich	0b3d4e7e75	merged changes in pcie	2020-08-06 21:35:00 -07:00
Alex Forencich	e54eb685b3	Update makefiles	2020-08-06 18:43:47 -07:00
Alex Forencich	bf589968fb	merged changes in eth	2020-08-06 18:32:31 -07:00
Alex Forencich	0d7a2dba2f	merged changes in pcie	2020-08-06 18:32:27 -07:00
Alex Forencich	77b9cace47	Update BAR configuration in testbenches	2020-07-28 19:01:53 -07:00
Alex Forencich	ffd04d2bb0	Cleanup	2020-07-28 19:00:33 -07:00
Alex Forencich	495178e1dc	Fix mask	2020-07-28 18:30:52 -07:00
Alex Forencich	e4566dc545	merged changes in pcie	2020-07-28 16:00:31 -07:00
Alex Forencich	d449be8fc5	Convert to 64 bit BARs	2020-07-24 16:54:57 -07:00
Alex Forencich	2a23be508a	Add 100G mqnic design for Alveo U50	2020-07-17 01:44:59 -07:00
Alex Forencich	deb895ff05	Add 10G mqnic design for Alveo U50	2020-07-17 01:44:28 -07:00
Alex Forencich	18f56fcb16	Remove extraneous signals	2020-07-17 00:57:47 -07:00
Alex Forencich	837a390567	Fix VCU118 CMAC reference clocks	2020-07-14 10:47:18 -07:00
Alex Forencich	20eac98bde	Clean up	2020-07-14 00:33:12 -07:00
Alex Forencich	e230fecb23	XDC clean up	2020-07-13 23:58:39 -07:00
Alex Forencich	9b7fa688d5	Add 100G mqnic design for Alveo U280	2020-07-12 11:33:28 -07:00
Alex Forencich	6433275139	Add 10G mqnic design for Alveo U280	2020-07-12 11:33:18 -07:00
Alex Forencich	f99736d4f5	Convert to TCL IP	2020-07-11 20:07:13 -07:00
Alex Forencich	5dd5f8bb3e	merged changes in pcie	2020-07-10 19:46:48 -07:00
Alex Forencich	7c10036183	merged changes in eth	2020-07-10 19:46:43 -07:00
Alex Forencich	0ff6282ed6	merged changes in axi	2020-07-10 19:46:37 -07:00
Alex Forencich	4e958096b2	Update driver model to set MTU registers	2020-05-01 19:19:56 -07:00
Alex Forencich	ae775a9386	Rewrite RX buffer management	2020-05-01 19:00:58 -07:00
Alex Forencich	8b535e54ac	Add MTU registers	2020-05-01 18:55:01 -07:00
Alex Forencich	ca0cbf4d93	Update parameters	2020-05-01 17:22:21 -07:00
Alex Forencich	1f76606667	Move TDMA registers	2020-05-01 16:55:57 -07:00
Alex Forencich	ded213460d	Rewrite TX buffer management	2020-05-01 14:29:52 -07:00
Alex Forencich	1c7b7937e5	Limit in-flight descriptor requests in TX engine	2020-04-30 23:37:41 -07:00
Alex Forencich	45ec6657b1	Limit in-flight descriptor requests in RX engine	2020-04-30 23:29:43 -07:00
Alex Forencich	31cec8d0c1	Fix cmac_pad frame truncation bug	2020-04-22 23:23:34 -07:00