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925 Commits

Author SHA1 Message Date
Alex Forencich
ca07a23afc fpga/common: Add extra non-ASYNC_REG registers on transceiver resets to permit replication 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-24 21:34:42 -08:00
Alex Forencich
0f86ea9bb1 fpga/common: Remove unnecessary reset from clock info register block 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-24 21:32:30 -08:00
Alex Forencich
1682389fd0 Remove recursively-expanded macros for module parameters in makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-17 16:24:52 -08:00
Alex Forencich
24c74b3003 merged changes in pcie 2023-02-17 16:20:00 -08:00
Alex Forencich
e7953da0c0 merged changes in eth 2023-02-17 16:19:50 -08:00
Alex Forencich
93ceea327e merged changes in axi 2023-02-17 16:19:45 -08:00
Alex Forencich
86e87c7c3b Fix PTP clock offset ns field width 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-17 15:47:47 -08:00
Alex Forencich
e872c6c749 Rework parameter handling in testbench makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-29 23:20:44 -08:00
Alex Forencich
90c703464d merged changes in pcie 2023-01-29 23:00:36 -08:00
Alex Forencich
d1ee73fea4 merged changes in eth 2023-01-29 23:00:30 -08:00
Alex Forencich
2158c4ef9c merged changes in axi 2023-01-29 23:00:23 -08:00
Alex Forencich
5b859b08a0 Use false path constraints for status signals that change infrequently 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-17 14:25:30 -08:00
Alex Forencich
79431bf221 merged changes in eth 2023-01-15 18:26:16 -08:00
Alex Forencich
6c58e950d3 fpga/mqnic: Add DRAM interface module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-19 16:47:02 -08:00
Alex Forencich
5b20e3ff87 fpga/mqnic: Use BUFG for HBM AXI reset 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-18 13:55:00 -08:00
Alex Forencich
aee97e4825 fpga/mqnic: Add performance-related MIG settings to config.tcl 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-17 23:16:19 -08:00
Alex Forencich
7198973383 fpga/mqnic: Support using only a subset of HBM ports, and distribute subset across available interface ports for best performance 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-17 23:03:36 -08:00
Alex Forencich
9969b957d5 fpga/mqnic: Clean up HBM configuration 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-17 22:56:12 -08:00
Alex Forencich
8672edfdb3 fpga/mqnic: Connect HBM MMCM reset input 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-17 22:51:49 -08:00
Alex Forencich
1dacc6b1fa fpga/mqnic: Fix HBM temp signal width; tie off temp and cattrip signals when HBM is disabled 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-17 22:49:38 -08:00
Alex Forencich
bbdb44ce01 fpga/mqnic/common: Clean up TCL timing constraints and update to handle clocks from OOC IP that are not constrained during synthesis 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-08 18:50:30 -08:00
Alex Forencich
c708bc45cd fpga/mqnic/fb2CG: Update testbench 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:23:28 -08:00
Alex Forencich
e7dc033c78 fpga/mqnic/DE10_Agilex: Add DMA bench target for Terasic DE10-Agilex 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:18:40 -08:00
Alex Forencich
9020e0f819 fpga/mqnic/ZCU106: Add DMA bench target for Xilinx ZCU106 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:16:48 -08:00
Alex Forencich
76298b6cae fpga/mqnic/ZCU102: Add DMA bench target for Xilinx ZCU102 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:16:27 -08:00
Alex Forencich
0b9b9510ae fpga/mqnic/XUPP3R: Add DMA bench target for BittWare XUP-P3R 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:15:57 -08:00
Alex Forencich
23a5cc07da fpga/mqnic/VCU1525: Add DMA bench target for Xilinx VCU1525 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:15:31 -08:00
Alex Forencich
6f49e42727 fpga/mqnic/VCU118: Add DMA bench target for Xilinx VCU118 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:15:15 -08:00
Alex Forencich
3483187403 fpga/mqnic/VCU108: Add DMA bench target for Xilinx VCU108 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:14:59 -08:00
Alex Forencich
014e810762 fpga/mqnic/NetFPGA_SUME: Add DMA bench target for NetFPGA SUME 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:14:32 -08:00
Alex Forencich
c306d20669 fpga/mqnic/Nexus_K3P_Q: Add DMA bench target for Cisco Nexus K3P-Q 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:14:02 -08:00
Alex Forencich
f9f4415e13 fpga/mqnic/Nexus_K3P_S: Add DMA bench target for Cisco Nexus K3P-S 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:13:47 -08:00
Alex Forencich
2672f39115 fpga/mqnic/Nexus_K35_S: Add DMA bench target for Cisco Nexus K35-S 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:13:15 -08:00
Alex Forencich
b915babce8 fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP: Add DMA bench target for Dini Group DNPCIe_40G_KU_LL_2QSFP 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:12:25 -08:00
Alex Forencich
76553e3bba fpga/mqnic/250_SoC: Add DMA bench target for BittWare 250-SoC 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:10:53 -08:00
Alex Forencich
df4857fe0b fpga/mqnic/ADM_PCIE_9V3: Add DMA bench target for Alpha Data ADM-PCIE-9V3 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:08:08 -08:00
Alex Forencich
5f9e33e8ab fpga/mqnic: Enable overtemp shutdown on all boards 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 15:23:23 -08:00
Alex Forencich
59911c5ba7 fpga/mqnic/Nexus_K3P_S: Switch Cisco Nexus K3P-S designs to use 10 MHz TCXO for PTP reference clock 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 14:33:32 -08:00
Alex Forencich
a0aa614362 fpga/mqnic/Nexus_K3P_Q: Switch Cisco Nexus K3P-Q designs to use 10 MHz TCXO for PTP reference clock 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 14:33:00 -08:00
Alex Forencich
4b7d51133f fpga/mqnic: Enable statistics counters on all targets 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 13:06:39 -08:00
Alex Forencich
e8aaadd102 fpga: Clean up top-level PCIe interface parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-04 23:56:56 -08:00
Alex Forencich
08f49d7e17 fpga/mqnic: Add missing DRP frequency parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-04 22:07:58 -08:00
Alex Forencich
3a7343ec6d fpga/mqnic: Add missing connections 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-04 22:03:21 -08:00
Alex Forencich
0644a12a48 fpga/mqnic: Remove extraneous top-level parameter RX_RSS_ENABLE from config.tcl scripts 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-03 21:32:51 -08:00
Alex Forencich
347a03b347 fpga/mqnic: Rework PCIe IP core configuration, fixes disrupted MSI-X settings with application section enabled and issues with PCIe class code on 7-series and UltraScale 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-03 18:16:12 -08:00
Alex Forencich
c5003d0c6d fpga/mqnic: Select advanced mode for Xilinx PCIe IP core config to access MSI-X settings 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-03 15:35:16 -08:00
Alex Forencich
ad18c19da9 fpga/mqnic: Fix default class code for UltraScale and 7-series devices 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-03 15:33:52 -08:00
Alex Forencich
5d1df56706 fpga/app/dma_bench: Update counter labels 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-03 15:29:58 -08:00
Alex Forencich
78363dd2d8 fpga/mqnic/AU280: Add DMA bench target for Alveo U280 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-01 17:52:17 -08:00
Alex Forencich
0e6c48f468 fpga/mqnic/AU50: Add DMA bench target for Alveo U50 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-01 17:51:44 -08:00