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24 Commits

Author SHA1 Message Date
Alex Forencich
54d0165f68 modules/mqnic: Register ports with devlink 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-13 16:40:27 -07:00
Alex Forencich
6b256f82d3 Generate pause frames on TX 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-10 23:22:50 -07:00
Alex Forencich
bed12ee774 Consolidate CQs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-10 17:52:34 -07:00
Alex Forencich
265035769a Reorganize queue control registers 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-07 01:19:19 -07:00
Alex Forencich
448fa8eb4c Use SPDX 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-26 11:44:57 -07:00
Alex Forencich
3c995dc8e0 Implement dynamic queue allocation in testbench and driver 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-02 21:23:30 -07:00
Alex Forencich
9834f8365c Rework resource management in testbenches, driver, and utils 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-01 22:04:43 -07:00
Alex Forencich
1c7ae0ee73 modules/mqnic: Return pointers directly and use ERR_PTR during object creation 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-30 21:57:32 -07:00
Alex Forencich
66f5b9fcc1 Clean up naming in testbenches, driver, and utils 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-30 21:48:34 -07:00
Alex Forencich
bb158d568f Add RX indirection table 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-10 15:05:32 -07:00
Alex Forencich
c2fea3a616 Add port register blocks with support for PHY link status reporting 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-04 09:03:37 -07:00
Alex Forencich
56641b3471 modules/mqnic: Export symbols 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-25 00:47:37 -07:00
Alex Forencich
e4de3c2fb5 modules/mqnic: Consistent naming of driver functions and structs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-24 23:01:15 -07:00
Alex Forencich
2bd8350276 Add RX queue mapping module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-23 00:12:22 -07:00
Alex Forencich
1b3caa1f0f Fix reg block enumeration to properly handle NULL register blocks 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-22 23:27:15 -07:00
Alex Forencich
cbd9d0dfc6 Expose port and scheduler block counts in IF control block; update driver model, driver, and userspace tools to handle scheduler blocks separately from ports 2022-03-28 17:23:27 -07:00
Alex Forencich
d506c9305a Fix pointer updating for correct teardown behavior 2022-01-16 00:04:53 -08:00
Alex Forencich
137a6778da Combine interface control blocks 2022-01-15 21:53:13 -08:00
Alex Forencich
a4a26e7bc4 Fix register accesses 2022-01-05 19:38:56 -08:00
Alex Forencich
ce21774f06 Register space reorganization 2021-12-29 22:31:46 -08:00
Alex Forencich
2091ef8c42 Fix dev_port assignment 2021-12-29 14:29:55 -08:00
Alex Forencich
8b219d3cad Fix I2C client forwarding to netdevs 2021-12-25 01:40:08 -08:00
Joachim Foerster
508b4cf39b modules/mqnic/: Make number of allocated queue entries configurable via module parameters 
This may be complemented or replaced by making use of the appropriate ethtool
API in the future, of course.

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
 2021-12-15 23:29:02 -08:00
Alex Forencich
11f31c896c Split interface from net_device 2021-12-12 17:28:43 -08:00