FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-16 08:12:53 +08:00
Code Issues Projects Releases Wiki Activity
3,255 Commits 1 Branch 0 Tags
Commit Graph

98 Commits

Author SHA1 Message Date
Alex Forencich
45a6250e43 Update FPGA ID list and adjust part matching to handle multiple parts with the same JTAG ID 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-12 19:09:56 -08:00
Alex Forencich
2a7d0e0947 Use new PTP time distribution subsystem 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-07 21:57:07 -08:00
Alex Forencich
6b256f82d3 Generate pause frames on TX 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-10 23:22:50 -07:00
Alex Forencich
9963674c61 Add flow control 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-09 19:01:36 -07:00
Alex Forencich
bed12ee774 Consolidate CQs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-10 17:52:34 -07:00
Alex Forencich
265035769a Reorganize queue control registers 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-07 01:19:19 -07:00
Alex Forencich
cc202ce45d utils: Add verbose option to mqnic-dump; hide disabled queues, scheduler state, and zero-valued statistics counters by default 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-27 23:31:28 -07:00
Alex Forencich
448fa8eb4c Use SPDX 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-26 11:44:57 -07:00
Alex Forencich
6ca5fbfd82 Merge PR #153 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-25 18:51:12 -07:00
Joachim Foerster
af22f5a43c utils/.gitignore: Minor, add mqnic-xcvr 
Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
 2023-06-22 11:06:13 +02:00
Joachim Foerster
bf09d80999 utils/Makefile: clean: Fix, also call target clean on libmqnic directory 
Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
 2023-06-22 11:06:12 +02:00
Alex Forencich
9834f8365c Rework resource management in testbenches, driver, and utils 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-01 22:04:43 -07:00
Alex Forencich
66f5b9fcc1 Clean up naming in testbenches, driver, and utils 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-30 21:48:34 -07:00
Alex Forencich
bb158d568f Add RX indirection table 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-10 15:05:32 -07:00
Alex Forencich
6cfd808823 utils: Dump statistics counters in mqnic-dump 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-23 17:38:28 -08:00
Alex Forencich
d3942da875 fpga: Add clock info register block 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-15 19:45:02 -07:00
Alex Forencich
7f1c714bc4 utils: Add mqnic-xcvr utility 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-29 12:02:50 -07:00
Alex Forencich
796ead9b1b utils: Fix PCI device path checks 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-27 14:26:37 -07:00
Alex Forencich
1eb04bb75b utils: Improve PTP clock period reporting 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-05 15:11:26 -07:00
Alex Forencich
c2fea3a616 Add port register blocks with support for PHY link status reporting 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-04 09:03:37 -07:00
Alex Forencich
698fd2f104 Consistent naming of library functions and structs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-24 22:51:37 -07:00
Alex Forencich
2bd8350276 Add RX queue mapping module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-23 00:12:22 -07:00
Alex Forencich
1b3caa1f0f Fix reg block enumeration to properly handle NULL register blocks 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-22 23:27:15 -07:00
Alex Forencich
c58585036e lib/mqnic: Add mqnic_print_fw_id 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-19 13:37:54 -07:00
Alex Forencich
e6c18cfb68 Move fpga_id into library 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-19 13:36:02 -07:00
Alex Forencich
a1cd110074 Peel off common software components into a static library 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-19 01:45:01 -07:00
Alex Forencich
edb545ca50 utils/mqnic-fw: Fix width detection for BPI flash 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-16 22:00:16 -07:00
Alex Forencich
f44641e91e utils: Add sanity check when reading SPI flash ID 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-16 15:23:17 -07:00
Alex Forencich
eb530475fb More expressive flash format register 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-15 18:38:01 -07:00
Alex Forencich
7be7b1cc9f utils/mqnic-fw: Confirm write and reset operations 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-15 18:17:04 -07:00
Alex Forencich
88679ef7eb utils/mqnic-fw: Add segment erase action 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-15 18:04:51 -07:00
Alex Forencich
09257457cb utils/mqnic-fw: Determine data width directly from control registers 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-15 16:15:11 -07:00
Alex Forencich
d9867948ec utils/mqnic-fw: Remove unused address width parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-15 15:54:03 -07:00
Alex Forencich
cf8aa506b2 utils: Always use 4-byte addresses for large SPI flash devices 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-15 13:13:59 -07:00
Alex Forencich
3b8643877d Support bare device name 2022-03-28 18:06:22 -07:00
Alex Forencich
cbd9d0dfc6 Expose port and scheduler block counts in IF control block; update driver model, driver, and userspace tools to handle scheduler blocks separately from ports 2022-03-28 17:23:27 -07:00
Alex Forencich
6daf1171b5 Improve ioctl implementation to support arbitrary number of regions 2022-03-26 00:24:02 -07:00
Alex Forencich
51877b2bfd Combined write and verify operation 2022-03-03 22:48:53 -08:00
Alex Forencich
d325d0df3e Minor cleanup 2022-03-03 22:48:24 -08:00
Alex Forencich
3d5395a7ca Update makefile 2022-03-03 22:46:18 -08:00
Alex Forencich
7fa621bddf Clean up types 2022-03-03 22:45:38 -08:00
Alex Forencich
e3799aa1bf Add missing dummy reads 2022-03-03 22:44:32 -08:00
Alex Forencich
d5f1da7f08 Print PCIe device ID, if available 2022-03-03 22:44:05 -08:00
Alex Forencich
137a6778da Combine interface control blocks 2022-01-15 21:53:13 -08:00
Alex Forencich
eba32ce8a5 Accept interface name and PCIe BDF when connecting to device 2022-01-08 15:32:50 -08:00
Alex Forencich
23f635f273 Clean up return code checks 2022-01-08 15:14:49 -08:00
Alex Forencich
136b0ee6ae Increase init delay for Alveo BMC 2022-01-05 22:42:36 -08:00
Alex Forencich
975ba91239 Fix register accesses 2022-01-05 19:38:46 -08:00
Alex Forencich
ce21774f06 Register space reorganization 2021-12-29 22:31:46 -08:00
Alex Forencich
23cd700a3f Refactor userspace init/teardown code 2021-12-24 13:49:41 -08:00