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Author SHA1 Message Date
Alex Forencich
c90d5141ac Add ethernet arbitrated mux module and testbench 2014-11-14 22:11:49 -08:00
Alex Forencich
acb7241f4b merged changes in axis 2014-11-14 17:48:59 -08:00
Alex Forencich
9bee01e74c Add ethernet mux and testbench 2014-11-14 17:48:51 -08:00
Alex Forencich
7c86999399 Minor reorganization 2014-11-13 16:26:07 -08:00
Alex Forencich
5205c8911b merged changes in axis 2014-11-13 16:12:39 -08:00
Alex Forencich
789c7da6d6 Fix parameter 2014-11-13 10:39:41 -08:00
Alex Forencich
698234c297 Update comments 2014-11-13 10:39:27 -08:00
Alex Forencich
8a46e6900c Update readme 2014-11-13 10:21:54 -08:00
Alex Forencich
bd90208153 Update readme 2014-11-13 10:19:46 -08:00
Alex Forencich
e2ca92b69a merged changes in axis 2014-11-13 10:11:23 -08:00
Alex Forencich
851aeb9309 Fix block parameter 2014-11-13 10:06:28 -08:00
Alex Forencich
5f0d23a3ad Add AXI arbitrated mux module and testbench 2014-11-13 02:01:45 -08:00
Alex Forencich
a8970e6e75 Change block parameter 2014-11-13 02:01:07 -08:00
Alex Forencich
a1633f27d8 Add arbiter module 2014-11-13 01:22:59 -08:00
Alex Forencich
3399f284b2 Add priority encoder 2014-11-12 23:59:02 -08:00
Alex Forencich
5c49ed6191 Add AXI stream demux and testbench 2014-11-12 19:21:28 -08:00
Alex Forencich
73a580df95 Update readme 2014-11-12 15:53:47 -08:00
Alex Forencich
5af6dc3501 Add AXI stream mux and testbench 2014-11-12 15:49:07 -08:00
Alex Forencich
aafacb372e Trim trailing spaces 2014-11-12 15:32:05 -08:00
Alex Forencich
3816eb3c20 Fix parameters 2014-11-12 02:06:18 -08:00
Alex Forencich
d6784d189d Update readme 2014-11-12 02:03:59 -08:00
Alex Forencich
7f8342ba1d merged changes in axis 2014-11-12 01:58:01 -08:00
Alex Forencich
a28a534bff Add AXI stream crosspoint module and testbench 2014-11-12 01:54:31 -08:00
Alex Forencich
7804272b2e Updated readme 2014-11-09 02:13:20 -08:00
Alex Forencich
10e0d7d1bb Add AXI async frame fifo and testbench 2014-11-08 21:29:39 -08:00
Alex Forencich
6fa46b6c57 Add AXI frame fifo and testbench 2014-11-08 21:07:47 -08:00
Alex Forencich
b232a6459d Remove counter from AXI fifo modules 2014-11-08 12:45:36 -08:00
Alex Forencich
a86541767f merged changes in axis 2014-11-08 00:35:34 -08:00
Alex Forencich
918ef8f76c Add AXI async FIFO and testbench 2014-11-08 00:23:23 -08:00
Alex Forencich
8214e2abf9 added axis as a subproject 
git-subtree-dir: lib/axis
git-subtree-mainline: d64445b9e057cf97ae8fd57fbe83c5505c6ba45c
git-subtree-split: ac2f7e546df3b7f4a936cdb4d558adc517c5ddb4
 2014-11-05 17:25:00 -08:00
Alex Forencich
d64445b9e0 Add git subdir script for axis lib 2014-11-05 17:24:48 -08:00
Alex Forencich
96c6fcd144 Remove AXI stream components 2014-11-05 16:59:59 -08:00
Alex Forencich
ac2f7e546d Adjust syntax for old Python 2 2014-11-05 16:40:27 -08:00
Alex Forencich
e8c43653e3 Adjust syntax for old Python 2 2014-11-05 16:33:33 -08:00
Alex Forencich
849f3c174a Add .travis.yml 2014-11-05 16:22:09 -08:00
Alex Forencich
0507fd4ca9 Update readme 2014-11-05 16:19:00 -08:00
Alex Forencich
588c2742e8 Separate out input mux in AXI frame joiner 2014-10-28 01:55:42 -07:00
Alex Forencich
af0dce33b1 Separate out input mux in AXI frame joiner 2014-10-28 01:55:42 -07:00
Alex Forencich
0f62d31fef Rework ARP datapath modules to separate output register 2014-10-28 01:55:36 -07:00
Alex Forencich
4474181549 Rework UDP datapath modules to separate output register 2014-10-28 01:55:29 -07:00
Alex Forencich
867b799ecd Rework IP datapath modules to separate output register 2014-10-28 01:00:52 -07:00
Alex Forencich
0e26b3a8a4 Put back lane shifting logic 2014-10-28 00:54:15 -07:00
Alex Forencich
205be7ed27 Rework AXI ethernet modules to separate output register 2014-10-23 00:05:06 -07:00
Alex Forencich
f827b5eafb Improve output register filling 2014-10-22 15:13:42 -07:00
Alex Forencich
0b8a36d5e7 Improve output register filling 2014-10-22 15:13:42 -07:00
Alex Forencich
5f14df216a Improve output register filling 2014-10-22 15:11:41 -07:00
Alex Forencich
d82ebcce17 Improve output register filling 2014-10-22 15:11:41 -07:00
Alex Forencich
a2a509884e Improve output register filling 2014-10-22 15:10:21 -07:00
Alex Forencich
c86ffa1202 Improve output register filling 2014-10-22 15:10:21 -07:00
Alex Forencich
47a8c35d5d Improve output register filling 2014-10-22 15:10:07 -07:00