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Author SHA1 Message Date
Alex Forencich
73728d1994 Adjust testbench timeouts 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-26 18:47:15 -08:00
Alex Forencich
8673038288 Update CI configuration 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-26 16:43:01 -08:00
Alex Forencich
28916a56cd Update CI configuration 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-26 16:41:36 -08:00
Alex Forencich
eda769d167 Update CI configuration 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-26 13:00:03 -08:00
Alex Forencich
7b2c99e731 Fix unaligned operation handling in AXI to AXIL adapter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-26 12:58:39 -08:00
Alex Forencich
211f674603 Fix unaligned operation handling in AXI adapter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-26 12:58:03 -08:00
Alex Forencich
3dc4ca92f6 Improve unaligned operation handling in AXIL adapter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-25 21:08:32 -08:00
Alex Forencich
3ac119305d Update CI configuration 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-25 19:10:50 -08:00
Alex Forencich
e6d8ed7992 Update CI configuration 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-25 19:10:09 -08:00
Alex Forencich
57803eeeb8 Remove deprecated assignments 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-24 15:07:45 -08:00
Alex Forencich
5b859b08a0 Use false path constraints for status signals that change infrequently 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-17 14:25:30 -08:00
Alex Forencich
f521fb6435 Update timing constraints to handle clocks from OOC IP that are not constrained during synthesis 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-17 13:40:36 -08:00
Alex Forencich
79431bf221 merged changes in eth 2023-01-15 18:26:16 -08:00
Alex Forencich
450765187e Update lfsr.v 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-15 12:36:03 -08:00
Alex Forencich
cb1dc8fb15 Optimize FCS verification in 10G/25G MAC modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-13 15:47:30 -08:00
Alex Forencich
7a0e88ffea Update vivado.mk 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-13 14:57:46 -08:00
Alex Forencich
f3d5e74527 Add RV901T example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-01 22:03:14 -08:00
Alex Forencich
713b138ece Fix timing of IDDR2 on Spartan 6 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-01 21:44:15 -08:00
Alex Forencich
a77c671920 merged changes in axis 2022-12-30 17:06:48 -08:00
Alex Forencich
786e971f40 Remove separate memory read register (it causes ISE to crash, and is not necessary for URAM inference) 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-29 23:54:17 -08:00
Alex Forencich
8c3df76b97 Fix signal name 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-27 18:26:58 -08:00
Alex Forencich
a1abc97e2a ISE does not support clog2 in localparam 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-27 18:26:47 -08:00
Alex Forencich
6c58e950d3 fpga/mqnic: Add DRAM interface module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-19 16:47:02 -08:00
Alex Forencich
5b20e3ff87 fpga/mqnic: Use BUFG for HBM AXI reset 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-18 13:55:00 -08:00
Alex Forencich
aee97e4825 fpga/mqnic: Add performance-related MIG settings to config.tcl 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-17 23:16:19 -08:00
Alex Forencich
7198973383 fpga/mqnic: Support using only a subset of HBM ports, and distribute subset across available interface ports for best performance 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-17 23:03:36 -08:00
Alex Forencich
9969b957d5 fpga/mqnic: Clean up HBM configuration 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-17 22:56:12 -08:00
Alex Forencich
8672edfdb3 fpga/mqnic: Connect HBM MMCM reset input 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-17 22:51:49 -08:00
Alex Forencich
1dacc6b1fa fpga/mqnic: Fix HBM temp signal width; tie off temp and cattrip signals when HBM is disabled 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-17 22:49:38 -08:00
Alex Forencich
bbdb44ce01 fpga/mqnic/common: Clean up TCL timing constraints and update to handle clocks from OOC IP that are not constrained during synthesis 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-08 18:50:30 -08:00
Alex Forencich
46bd4302de Update async FIFO timing constraints to handle clocks from OOC IP that are not constrained during synthesis 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-08 18:49:21 -08:00
Alex Forencich
c708bc45cd fpga/mqnic/fb2CG: Update testbench 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:23:28 -08:00
Alex Forencich
e7dc033c78 fpga/mqnic/DE10_Agilex: Add DMA bench target for Terasic DE10-Agilex 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:18:40 -08:00
Alex Forencich
9020e0f819 fpga/mqnic/ZCU106: Add DMA bench target for Xilinx ZCU106 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:16:48 -08:00
Alex Forencich
76298b6cae fpga/mqnic/ZCU102: Add DMA bench target for Xilinx ZCU102 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:16:27 -08:00
Alex Forencich
0b9b9510ae fpga/mqnic/XUPP3R: Add DMA bench target for BittWare XUP-P3R 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:15:57 -08:00
Alex Forencich
23a5cc07da fpga/mqnic/VCU1525: Add DMA bench target for Xilinx VCU1525 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:15:31 -08:00
Alex Forencich
6f49e42727 fpga/mqnic/VCU118: Add DMA bench target for Xilinx VCU118 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:15:15 -08:00
Alex Forencich
3483187403 fpga/mqnic/VCU108: Add DMA bench target for Xilinx VCU108 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:14:59 -08:00
Alex Forencich
014e810762 fpga/mqnic/NetFPGA_SUME: Add DMA bench target for NetFPGA SUME 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:14:32 -08:00
Alex Forencich
c306d20669 fpga/mqnic/Nexus_K3P_Q: Add DMA bench target for Cisco Nexus K3P-Q 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:14:02 -08:00
Alex Forencich
f9f4415e13 fpga/mqnic/Nexus_K3P_S: Add DMA bench target for Cisco Nexus K3P-S 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:13:47 -08:00
Alex Forencich
2672f39115 fpga/mqnic/Nexus_K35_S: Add DMA bench target for Cisco Nexus K35-S 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:13:15 -08:00
Alex Forencich
b915babce8 fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP: Add DMA bench target for Dini Group DNPCIe_40G_KU_LL_2QSFP 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:12:25 -08:00
Alex Forencich
76553e3bba fpga/mqnic/250_SoC: Add DMA bench target for BittWare 250-SoC 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:10:53 -08:00
Alex Forencich
df4857fe0b fpga/mqnic/ADM_PCIE_9V3: Add DMA bench target for Alpha Data ADM-PCIE-9V3 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 17:08:08 -08:00
Alex Forencich
5f9e33e8ab fpga/mqnic: Enable overtemp shutdown on all boards 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 15:23:23 -08:00
Alex Forencich
59911c5ba7 fpga/mqnic/Nexus_K3P_S: Switch Cisco Nexus K3P-S designs to use 10 MHz TCXO for PTP reference clock 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 14:33:32 -08:00
Alex Forencich
a0aa614362 fpga/mqnic/Nexus_K3P_Q: Switch Cisco Nexus K3P-Q designs to use 10 MHz TCXO for PTP reference clock 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 14:33:00 -08:00
Alex Forencich
4b7d51133f fpga/mqnic: Enable statistics counters on all targets 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-06 13:06:39 -08:00