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Author SHA1 Message Date
Alex Forencich
938479c246 MAC RX timing optimizations 2019-06-16 00:36:50 -07:00
Alex Forencich
27999924a0 Update VCU108 example designs 2019-06-15 17:35:49 -07:00
Alex Forencich
3684ccafb2 Make use of blocking statements consistent 2019-06-15 16:56:45 -07:00
Alex Forencich
b2cacc4e94 Update readme 2019-06-14 00:26:07 -07:00
Alex Forencich
d96a5a449a Update ARP cache testbench 2019-06-14 00:01:51 -07:00
Alex Forencich
ce13522085 Implement ARP cache clear 2019-06-14 00:01:13 -07:00
Alex Forencich
b41ab00381 Initialize ARP cache 2019-06-13 23:45:17 -07:00
Alex Forencich
296744b37e Make use of blocking statements consistent 2019-06-12 23:31:03 -07:00
Alex Forencich
7ccd520d2c merged changes in axis 2019-06-10 17:45:02 -07:00
Alex Forencich
ced2df141c Add false path for async FIFO implementation in distributed RAM 2019-06-10 17:40:30 -07:00
Alex Forencich
75d9154d32 Reduce extraneous warnings from get_cells 2019-06-10 17:39:18 -07:00
Alex Forencich
6eff2f0030 Decouple transmit PTP tag enable and transmit PTP timestamp enable 2019-06-09 22:03:24 -07:00
Alex Forencich
20bb430ae9 merged changes in axis 2019-06-09 18:59:03 -07:00
Alex Forencich
ccc15324a6 Fix bad frame mask 2019-06-09 18:46:49 -07:00
Alex Forencich
2794c315e8 Fix synthesizer complaints 2019-06-08 17:36:09 -07:00
Alex Forencich
82fe5a6bdd Add PTP timestamp capture logic to MACs 2019-06-07 16:38:36 -07:00
Alex Forencich
659aa67481 Pack start packet strobes into the same signal 2019-06-06 17:13:14 -07:00
Alex Forencich
2efcfdb0a0 Add PTP clock simulation model 2019-06-03 19:08:16 -07:00
Alex Forencich
e181ea5abc Add PTP clock module and testbench 2019-06-03 19:00:28 -07:00
Alex Forencich
352f52e159 Add flash target to Arty example design 2019-05-27 01:02:55 -07:00
Alex Forencich
3da3725429 Disable bit slipping when RX PRBS check is enabled 2019-05-16 23:22:47 -07:00
Alex Forencich
249f9d9df4 Update example designs 2019-05-10 22:55:44 -07:00
Alex Forencich
79ec137243 Add PRBS31 generation and checking to 10G PHY 2019-05-10 20:28:45 -07:00
Alex Forencich
e34c72da1f Add missing parameter 2019-05-10 17:23:55 -07:00
Alex Forencich
b7d297850c Move 10G PHY interface logic into separate modules 2019-05-10 14:56:18 -07:00
Alex Forencich
2abb413854 Fix signal name 2019-05-02 20:30:37 -07:00
Alex Forencich
1d61626785 Add KC705 GMII example design 2019-05-02 19:29:47 -07:00
Alex Forencich
8e969aa14c Add FIFO/width adapter wrapper modules 2019-04-26 18:38:25 -07:00
Alex Forencich
e3fcb0fa1d Test shorter frames 2019-04-26 18:36:09 -07:00
Alex Forencich
696c634726 Add rx_bad_block outputs 2019-04-17 00:16:45 -07:00
Alex Forencich
18d6aab16d Update readme 2019-04-03 22:32:06 -07:00
Alex Forencich
978fdce95c Minor fixes 2019-04-03 20:57:10 -07:00
Alex Forencich
1bec485766 Fix constants 2019-04-03 11:48:09 -07:00
Alex Forencich
5428d81fd6 Update AXI stream switch instances 2019-03-28 23:56:06 -07:00
Alex Forencich
9d21bf0f7c merged changes in axis 2019-03-28 23:51:06 -07:00
Alex Forencich
a9c7946368 Change parameter concatenation to increments of DEST_WIDTH 2019-03-28 23:49:04 -07:00
Alex Forencich
0008956828 Add Arty example design 2019-03-28 19:38:55 -07:00
Alex Forencich
8e2d936884 Add MII PHY interface, MAC wrappers, and testbenches 2019-03-28 19:18:03 -07:00
Alex Forencich
0ca8c9a59b Update example design timing constraints 2019-03-28 17:59:30 -07:00
Alex Forencich
e120a85607 Use correct clock 2019-03-28 17:56:55 -07:00
Alex Forencich
58201866f3 Add timing constraints 2019-03-28 17:53:51 -07:00
Alex Forencich
efab3d87a3 merged changes in axis 2019-03-28 16:35:19 -07:00
Alex Forencich
ad3905ac4d Account for more merged registers 2019-03-28 16:33:01 -07:00
Alex Forencich
d16d291d5e Upgrade example design IP cores 2019-03-28 16:30:34 -07:00
Alex Forencich
8285f94eaa Rename tx_sync regs 2019-03-28 16:27:33 -07:00
Alex Forencich
3eaed305f5 Connect TX underflow status outputs 2019-03-28 16:27:15 -07:00
Alex Forencich
edcfd0dc40 Prevent SRL inference in synchronizers 2019-03-28 12:36:32 -07:00
Alex Forencich
f66955cec0 merged changes in axis 2019-03-27 23:55:35 -07:00
Alex Forencich
e938844783 Account for merged registers 2019-03-27 23:54:48 -07:00
Alex Forencich
d651cb72de merged changes in axis 2019-03-26 18:49:15 -07:00