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Author SHA1 Message Date
Alex Forencich
8d9ed665d7 Use logical operator instead of bitwise 2018-12-09 00:04:56 -08:00
Alex Forencich
cadd1bcb50 Match width 2018-12-09 00:04:30 -08:00
Alex Forencich
aa6991a4a5 Bitwise operators instead of generate 2018-12-09 00:03:09 -08:00
Alex Forencich
3d90e80da8 Fix frame FIFO full logic bug 2018-12-09 00:01:38 -08:00
Alex Forencich
f9a5e6803b Add backpressure tests 2018-12-08 23:59:57 -08:00
Alex Forencich
f45a3ef5e0 Change cycle to segment 2018-12-03 12:40:06 -08:00
Alex Forencich
203771a5b8 merged changes in axis 2018-11-28 14:18:56 -08:00
Alex Forencich
a72d7bd260 Fix generate statement 2018-11-28 14:18:09 -08:00
Alex Forencich
fe8a4f9df3 Use constants for control characters 2018-11-11 00:18:32 -08:00
Alex Forencich
6a4b2699ea End frame reception on any control character 2018-11-11 00:11:27 -08:00
Alex Forencich
25e196e18b Insert idle characters 2018-11-10 18:56:50 -08:00
Alex Forencich
b195c6450b Add IFG parameter 2018-11-10 18:23:44 -08:00
Alex Forencich
a49b78b3c3 Add width asserts 2018-11-10 18:23:31 -08:00
Alex Forencich
b6c8cc7125 Append termination control character 2018-11-10 18:16:30 -08:00
Alex Forencich
0159376cda Simplify IFG count handling 2018-11-10 17:35:31 -08:00
Alex Forencich
d59a0553bd Change start character handling 2018-11-09 16:51:54 -08:00
Alex Forencich
261ad46a8a Add enable signals to xgmii model 2018-11-09 16:47:19 -08:00
Alex Forencich
6b85aed564 Any control characters in packet considered an error 2018-11-08 13:34:32 -08:00
Alex Forencich
ebe31e811c Use parameters for control characters 2018-11-08 13:15:47 -08:00
Alex Forencich
e882ed143f Update example designs 2018-11-08 09:20:33 -08:00
Alex Forencich
0a6bee6d69 Update example designs 2018-11-08 09:17:29 -08:00
Alex Forencich
29eccbc290 Update readme 2018-11-07 23:26:11 -08:00
Alex Forencich
6b1b36ded6 Assert header ready earlier if possible 2018-11-07 23:10:07 -08:00
Alex Forencich
b223c94adb Use registered header 2018-11-07 23:08:40 -08:00
Alex Forencich
d2fedc4134 Rename ports 2018-11-07 22:35:06 -08:00
Alex Forencich
b3f50ac2c7 Fix comments 2018-11-02 00:40:15 -07:00
Alex Forencich
98fc042489 Convert generated udp_demux to verilog parametrized module 2018-11-02 00:39:52 -07:00
Alex Forencich
81e9aa0c77 Convert generated ip_demux to verilog parametrized module 2018-11-02 00:25:23 -07:00
Alex Forencich
18c4214edb Convert generated eth_demux to verilog parametrized module 2018-11-02 00:23:31 -07:00
Alex Forencich
470ab887d9 Update mux instances 2018-11-01 00:59:14 -07:00
Alex Forencich
fea1186f57 Convert generated udp_arb_mux to verilog parametrized module 2018-11-01 00:48:26 -07:00
Alex Forencich
554e0a5380 Convert generated ip_arb_mux to verilog parametrized module 2018-11-01 00:40:09 -07:00
Alex Forencich
96cefbe0c1 Convert generated eth_arb_mux to verilog parametrized module 2018-10-31 21:42:28 -07:00
Alex Forencich
67025121ab Convert generated udp_mux to verilog parametrized module 2018-10-31 18:09:44 -07:00
Alex Forencich
f20312b199 Convert generated ip_mux to verilog parametrized module 2018-10-31 18:08:39 -07:00
Alex Forencich
d28d459d70 Convert generated eth_mux to verilog parametrized module 2018-10-31 15:48:12 -07:00
Alex Forencich
68abccd0a1 Workaround for MyHDL race condition 2018-10-31 13:42:33 -07:00
Alex Forencich
c08026277e Fix source pause logic 2018-10-31 13:42:08 -07:00
Alex Forencich
7d6889add6 Update example designs 2018-10-30 21:32:32 -07:00
Alex Forencich
6ffdc5f53d merged changes in axis 2018-10-30 17:36:40 -07:00
Alex Forencich
8d564b1074 Convert localparam to parameter as Vivado does not like clog2 in localparams 2018-10-30 17:35:38 -07:00
Alex Forencich
733044b0df Work around MyHDL sync race condition 2018-10-30 11:59:09 -07:00
Alex Forencich
20017c04b9 Work around MyHDL cosimulation race condition 2018-10-30 11:58:53 -07:00
Alex Forencich
ad8828d5b7 Update FIFO instances 2018-10-30 11:58:06 -07:00
Alex Forencich
e89097c8b1 merged changes in axis 2018-10-25 16:07:04 -07:00
Alex Forencich
be51f2b472 Update FIFO instantiations 2018-10-25 16:06:32 -07:00
Alex Forencich
ded363b471 Rename status outputs 2018-10-25 15:36:34 -07:00
Alex Forencich
ebe9d17bd5 Update readme 2018-10-25 14:30:42 -07:00
Alex Forencich
ed4a2d73c2 Add axis_pipeline_register module 2018-10-25 14:29:35 -07:00
Alex Forencich
ceedd0f8f5 Update readme 2018-10-25 14:27:24 -07:00