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Author SHA1 Message Date
Alex Forencich
01badce3a1 Remove unnecessary resets 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-01 18:30:32 -07:00
Alex Forencich
49513b45d4 Merge AU200, AU250, and VCU1525 designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-10-12 22:51:07 -07:00
Alex Forencich
e84da8dbfb Update HTG-9200 readmes 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-26 23:12:52 -07:00
Alex Forencich
b5d1fadb7e Add makefiles for VU13P variant of HTG-9200 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-26 15:07:16 -07:00
Alex Forencich
5ff1e17a29 Add missing assign to frame_min_count_reg in axis_baser_tx_64 module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-24 13:35:29 -07:00
Alex Forencich
90e6dfc638 Use phase detector in PTP CDC module for coarse period tuning, use 9 LSBs of timestamp for fine sync to avoid rollover corrections, reduce FNS comparison width to 4 bits 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-23 14:58:44 -07:00
Alex Forencich
a9e3d3cae8 Wait longer to ensure PTP CDC module has fully stabilized in MAC testbenches 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-23 14:52:48 -07:00
Alex Forencich
f9ae6da8bd Improve PTP CDC module testbench 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-23 14:33:14 -07:00
Alex Forencich
5a37442706 Merge FNS registers into NS registers in PTP CDC module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-22 22:52:59 -07:00
Alex Forencich
b0a4d75fd9 Remove extraneous code 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-22 01:08:01 -07:00
Alex Forencich
4a32c86f07 Match integrator width to period register width in PTP CDC module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-22 01:07:43 -07:00
Alex Forencich
cf441f004d Rename source sync signals in PTP CDC module for consistency 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-22 01:07:12 -07:00
Alex Forencich
4b1f48ab5b Parameter clean-up in PTP CDC module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-21 16:34:05 -07:00
Alex Forencich
aad30d09a1 Make FNS_WIDTH an internal parameter in PTP CDC module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-21 16:30:29 -07:00
Alex Forencich
98b4fbb56d Remove USE_SAMPLE_CLOCK parameter in PTP CDC module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-18 16:58:02 -07:00
Alex Forencich
060e55b915 Wait for correct PTP CDC instance to lock 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-18 16:39:30 -07:00
Alex Forencich
b316c6764e Use quad wrappers in ExaNIC X25 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 12:44:50 -07:00
Alex Forencich
f9eda00d68 Use quad wrappers in ExaNIC X10 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 12:43:29 -07:00
Alex Forencich
dc58b2447f Use quad wrappers in ZCU102 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 12:42:39 -07:00
Alex Forencich
d5df47d8b0 Use quad wrappers in ZCU106 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 12:42:04 -07:00
Alex Forencich
4618edcd8e Use quad wrappers in VCU108 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 01:15:29 -07:00
Alex Forencich
72de6c653a Use quad wrappers in AU50 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 01:09:00 -07:00
Alex Forencich
66987c8f62 Use quad wrappers in AU280 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 01:08:32 -07:00
Alex Forencich
22f327b35f Use quad wrappers in AU250 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 01:07:30 -07:00
Alex Forencich
65361d157b Use quad wrappers in AU200 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 01:06:28 -07:00
Alex Forencich
bd06e57764 Use quad wrappers in VCU1525 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 01:05:23 -07:00
Alex Forencich
c673ddbc14 Use quad wrappers in fb2CG@KU15P example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 00:37:44 -07:00
Alex Forencich
5d61059488 Use quad wrappers in ADM-PCIE-9V3 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 00:36:39 -07:00
Alex Forencich
1e88ed3d2e Update readme 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-25 23:12:59 -07:00
Alex Forencich
68736d02ae Add 10G/25G design for Arista 7132LB-48Y4C switch 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-25 23:06:49 -07:00
Alex Forencich
351ec79fef Use quad wrappers in VCU118 example designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-25 01:27:53 -07:00
Alex Forencich
75c2cc0acc Use quad wrappers in HTG9200 example designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-25 01:24:26 -07:00
Alex Forencich
aaeeb05ac0 Fix PHY configuration connections 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-25 00:09:38 -07:00
Alex Forencich
fa05d4ff3c Add TX and RX enable inputs to MACs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-24 01:24:33 -07:00
Alex Forencich
20c542051d Use cfg prefix for configuration signals 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-22 17:14:52 -07:00
Alex Forencich
f92a94d278 merged changes in axis 2023-08-16 16:19:04 -07:00
Alex Forencich
7823b916bf Implement MARK_WHEN_FULL option in FIFOs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-16 12:50:12 -07:00
Alex Forencich
6020d09214 Reorganize FIFO write logic 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-14 18:55:02 -07:00
Alex Forencich
c3cd676c5d Test DROP_WHEN_FULL parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-14 16:59:57 -07:00
Alex Forencich
c4f298de6f Add overflow test, previous test is actually an oversize frame test 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-14 16:59:30 -07:00
Alex Forencich
330d6f41fc Send more data in stress tests 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-14 16:59:14 -07:00
Alex Forencich
3a665f0ded Compute DEPTH based on FIFO data width 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-14 16:58:35 -07:00
Alex Forencich
7febd080c9 Use FIFO depth in overflow test 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-14 16:58:22 -07:00
Alex Forencich
ac2c0fdac8 Read configuration directly from DUT 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-14 16:57:30 -07:00
Alex Forencich
62c2148c8f Add pause functionality to FIFO modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-14 16:57:16 -07:00
Alex Forencich
e308c9559a Rewrite width converter to reduce resource consumption 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-14 16:56:54 -07:00
Alex Forencich
31bac4e21f Reorganize FIFO adapter wrappers 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-14 16:56:33 -07:00
Alex Forencich
d6fc68947b Procedural generation of testbench drivers 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-27 20:25:08 -07:00
Alex Forencich
6b00ff29c8 merged changes in axis 2023-07-27 01:45:14 -07:00
Alex Forencich
1628a1a043 Reorganize pipeline FIFO to facilitate placement constraints 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-27 01:43:36 -07:00