Alex Forencich
|
00858212c6
|
Placeholder values for flow control credit outputs
|
2019-12-06 19:16:05 -08:00 |
|
Alex Forencich
|
e7bd0a62f1
|
Implement RQ sequence numbers in Ultrascale models
|
2019-11-25 18:07:49 -08:00 |
|
Alex Forencich
|
b2c5004962
|
Fix discontinue masks
|
2019-11-23 00:20:21 -08:00 |
|
Alex Forencich
|
39200d84cb
|
Update simulation models to support 512 bit interface
|
2019-10-14 15:45:41 -07:00 |
|
Alex Forencich
|
5e9254d519
|
Check is_eof_0 in RCSink
|
2019-10-12 18:58:27 -07:00 |
|
Alex Forencich
|
9b5a5db4d1
|
Add USPcieFrame intermediate format
|
2019-10-12 18:01:39 -07:00 |
|
Alex Forencich
|
603a6e18e2
|
Fix RC channel sideband byte enables
|
2019-10-11 14:16:44 -07:00 |
|
Alex Forencich
|
295b6a507e
|
Use constants instead of magic numbers
|
2019-10-01 17:30:09 -07:00 |
|
Alex Forencich
|
3817736aa1
|
Use constants instead of magic numbers
|
2019-10-01 17:24:18 -07:00 |
|
Alex Forencich
|
1b91200a4a
|
Implement error code
|
2019-10-01 17:17:42 -07:00 |
|
Alex Forencich
|
b2d9a6a77f
|
Add constants
|
2019-10-01 17:15:15 -07:00 |
|
Alex Forencich
|
f92c1ea980
|
Reorder capability registrations
|
2019-02-28 23:46:39 -08:00 |
|
Alex Forencich
|
9f36acebc2
|
Print TLP payloads in hex
|
2019-01-28 18:17:21 -08:00 |
|
Alex Forencich
|
5a02ba2cb1
|
Use yield from more consistently
|
2018-10-23 21:24:39 -07:00 |
|
Alex Forencich
|
ab82ea5296
|
Match IP core ordering
|
2018-10-16 18:02:28 -07:00 |
|
Alex Forencich
|
6f9c2a1ed2
|
Add MSI support to Ultrascale PCIe model
|
2018-10-15 14:18:27 -07:00 |
|
Alex Forencich
|
35ccc2ffd5
|
Add pause signals
|
2018-10-15 14:17:00 -07:00 |
|
Alex Forencich
|
8ada97200f
|
Update signal widths
|
2018-10-15 13:41:29 -07:00 |
|
Alex Forencich
|
76dccafe0e
|
Consolidate MSI capability objects
|
2018-10-15 00:05:37 -07:00 |
|
Alex Forencich
|
c047716ae8
|
The only locked completions are for locked memory reads
|
2018-10-06 17:28:21 -07:00 |
|
Alex Forencich
|
2059e3b16f
|
Generate is_eof_0
|
2018-10-06 17:27:16 -07:00 |
|
Alex Forencich
|
a2a43dd11d
|
Fix parity polarity
|
2018-10-06 17:00:51 -07:00 |
|
Alex Forencich
|
2fef5c51df
|
Add PcieId object
|
2018-10-01 15:41:00 -07:00 |
|
Alex Forencich
|
4eb0ab240d
|
Add fmt_type property to TLP
|
2018-09-30 19:14:19 -07:00 |
|
Alex Forencich
|
16fdbba010
|
Fix RC packer bug
|
2018-09-28 01:06:36 -07:00 |
|
Alex Forencich
|
c57ef057ee
|
Initial commit
|
2018-09-25 19:50:57 -07:00 |
|