31 Commits

Author	SHA1	Message	Date
Alex Forencich	062495b780	Remove redundant parameter PCIE_EXT_TAG_ENABLE	2021-02-25 18:20:08 -08:00
Alex Forencich	8294eecd65	Remove redundant parameter PCIE_TAG_WIDTH	2021-02-25 18:10:59 -08:00
Alex Forencich	8cfbe18335	Use FIFO for op tag management in PCIe read DMA modules	2021-02-25 16:30:23 -08:00
Alex Forencich	40a191a06d	Add output FIFO and write done tracking to ultrascale PCIe read DMA interface	2021-02-24 13:50:05 -08:00
Alex Forencich	070689692d	Add wr_done signal to RAM model and placeholders to DMA components	2021-02-24 13:47:53 -08:00
Alex Forencich	93e2769269	Make 64-bit-only states no-ops for other interface widths	2021-02-14 15:17:28 -08:00
Alex Forencich	a78674c06a	Refactor TLP header and tuser computation	2021-02-14 11:16:25 -08:00
Alex Forencich	f567db764b	Rewrite 4K address boundary crossing checks	2020-11-11 23:54:39 -08:00
Alex Forencich	8045992eb6	Remove extraneous code	2020-07-27 22:29:04 -07:00
Alex Forencich	1f523f0bb4	Remove unused reg	2020-07-26 21:39:10 -07:00
Alex Forencich	dd97d2d749	Minor refactoring	2020-07-25 22:09:30 -07:00
Alex Forencich	566dfa07e7	Read DMA timing optimizations	2020-03-26 14:34:48 -07:00
Alex Forencich	08d92fd138	Add pipeline stage for memory write generation to improve completion handling throughput	2020-03-24 21:58:48 -07:00
Alex Forencich	f8ce39c585	Timing optimization	2020-03-24 19:41:02 -07:00
Alex Forencich	37934485af	Timing optimization for ram_wrap computation	2020-02-28 13:22:35 -08:00
Alex Forencich	983610d6d9	Timing optimization for mask computation	2020-02-28 13:02:26 -08:00
Alex Forencich	092c72ba66	Compute req_last_tlp in advance	2020-02-27 18:19:45 -08:00
Alex Forencich	18bf537f4f	Fix register size	2020-02-27 15:47:18 -08:00
Alex Forencich	a00589e5a3	Timing optimizations	2020-02-27 15:24:24 -08:00
Alex Forencich	ec2ceb8e56	Timing optimizations	2020-01-24 13:51:30 -08:00
Alex Forencich	7567db1818	Add credit-based flow control to DMA cores	2019-12-06 23:24:36 -08:00
Alex Forencich	f3a6cec13a	Use nonblocking assign	2019-12-03 15:47:58 -08:00
Alex Forencich	4c8fcef230	Add RQ sequence number inputs, TX_LIMIT parameter to ultrascale read DMA modules	2019-11-26 16:30:30 -08:00
Alex Forencich	bbcdcc17bc	Rename OP_TAG_WIDTH to OP_TABLE_SIZE	2019-11-25 14:59:53 -08:00
Alex Forencich	ee532a2472	Check tag count based on target device	2019-11-15 14:57:23 -08:00
Alex Forencich	c43a3eb41a	Fix latch inference	2019-10-22 16:03:58 -07:00
Alex Forencich	edfb962bf5	Byte enable computation optimizations	2019-10-17 11:41:56 -07:00
Alex Forencich	19ae70dcaa	Fix bad optimization	2019-10-16 00:30:10 -07:00
Alex Forencich	3a791afd37	Update DMA interface modules to support 512 bit interface	2019-10-14 16:23:18 -07:00
Alex Forencich	89ff925545	Timing optimizations	2019-10-14 14:00:55 -07:00
Alex Forencich	fdd7faef4f	Add Xilinx Ultrascale PCIe DMA interface modules and testbenches	2019-10-12 23:03:42 -07:00