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47 Commits

Author SHA1 Message Date
Alex Forencich
0644a12a48 fpga/mqnic: Remove extraneous top-level parameter RX_RSS_ENABLE from config.tcl scripts 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-03 21:32:51 -08:00
Alex Forencich
d3942da875 fpga: Add clock info register block 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-15 19:45:02 -07:00
Alex Forencich
d0cc106783 fpga: Remove redundant RX_RSS_ENABLE parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-13 17:10:25 -07:00
Alex Forencich
01df80df86 fpga/mqnic: Disable MIGs by default 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-12 23:57:27 -07:00
Alex Forencich
5e52a52f5e fpga/mqnic: Add MIGs and HBM controllers for most boards 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-12 19:00:49 -07:00
Alex Forencich
eb990643f2 fpga/mqnic: various minor cleanup 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-12 17:12:07 -07:00
Alex Forencich
5f1e74b0e1 Add PROJECT variable, remove multiple stem matches 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-11 13:33:09 -07:00
Alex Forencich
7017e7d49b Explicitly set top module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-11 12:29:01 -07:00
Alex Forencich
ceb6a9ca06 Update clean target 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-11 12:26:39 -07:00
Alex Forencich
9c98f12392 Write debug probes file alongside bit file 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-10 23:37:54 -07:00
Alex Forencich
9628401780 Normalize output file location 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-10 21:47:53 -07:00
Alex Forencich
d7904b8007 fpga: Add support for IRQ rate limiting 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-04 15:24:40 -07:00
Alex Forencich
1486da601f fpga: Add clock period parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-04 12:03:35 -07:00
Alex Forencich
647a168299 Enable more peripherals in Zynq designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-16 18:49:02 -07:00
Alex Forencich
171c2a9a69 fpga/mqnic/ZCU106/fpga_zynqmp: Remove SI570 workaround 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-15 23:54:02 -07:00
Alex Forencich
ef5b2449dc Add stretched PTP PPS output 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:25:58 -07:00
Alex Forencich
b1240bdcae Remove extraneous wires 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:25:10 -07:00
Alex Forencich
e0d92172d3 Separate PTP TX clock input 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:24:41 -07:00
Alex Forencich
33b798540e Change hex format in makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-09 14:20:48 -07:00
Alex Forencich
5da044826d Add board-level configuration parameter for TDMA BER module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-18 11:25:58 -07:00
Alex Forencich
ed2d34153d Use PHY rx_status signal for link status detection 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-17 00:46:05 -07:00
Alex Forencich
835f0d38f0 Update PTP subsystem to use separate clock for improved stability 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-06 17:46:16 -07:00
Alex Forencich
c2fea3a616 Add port register blocks with support for PHY link status reporting 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-04 09:03:37 -07:00
Alex Forencich
cfdd6f5455 Decouple transmit completion handling from PTP timestamping 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-01 17:41:47 -07:00
Alex Forencich
53f3547ef5 Rework hierarchy to move port-specific logic out of mqnic_core and into mqnic_interface and new port-level modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-29 14:32:57 -07:00
Alex Forencich
d5c2566dff Add statistics collection for AXI DMA IF 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-23 13:12:50 -07:00
Alex Forencich
2bd8350276 Add RX queue mapping module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-23 00:12:22 -07:00
Alex Forencich
7f8bbe30de Add application ID 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-21 13:15:45 -07:00
Alex Forencich
ba70498518 fpga: Add DMA immediate connections and parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-20 15:00:58 -07:00
Alex Forencich
f687aba432 fpga/mqnic: Update designs to use port mapping modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-13 01:37:10 -07:00
Alex Forencich
57905a5ef9 fpga/mqnic/ZCU106/fpga_zynqmp: Rewrite zynq PS TCL script, rework PS clock settings, switch to 300 MHz PL clock 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-11 12:25:51 -07:00
Alex Forencich
72d8583235 fpga/mqnic/ZCU106/fpga_zynqmp: Remove unused I2C interface 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-11 10:54:58 -07:00
Alex Forencich
c5d5fe8a64 fpga/mqnic: Remove unused wires 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-09 23:02:44 -07:00
Alex Forencich
1bb7053a68 ZCU106/fpga_zynqmp: Add integration test 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-07 21:42:01 -07:00
Alex Forencich
5f7c051b5b ZCU106/fpga_zynqmp: Sync module parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-07 21:41:06 -07:00
Alex Forencich
2eb4e5c4bd ZCU106/fpga_zynqmp/ps/petalinux/: Enable PTP in kernel and add linuxptp package 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-07 19:23:36 -07:00
Joachim Foerster
eb17563097 ZCU106/fpga_zynqmp/ps/petalinux/: Add shortcut Makefile target "build-boot" to build PetaLinux including boot files in one step 
Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
 2022-04-07 18:41:05 +02:00
Joachim Foerster
2252308dc2 ZCU106/fpga_zynqmp/: README: Provide more information on how to build and test 
Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
 2022-04-07 18:41:05 +02:00
Joachim Foerster
1191908e68 ZCU106/fpga_zynqmp/ps/petalinux/: rootfs: Enable and include layer meta-corundum and its recipes 
Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
 2022-04-07 18:41:05 +02:00
Joachim Foerster
442a24c5a7 ZCU106/fpga_zynqmp/ps/petalinux/: rootfs: Include various kernel module and network device tools 
- kmod (for modinfo)
- ethtool
- net-tools (for arp)
- iputils-ping (for ping; Busybox' ping does not support flood ping option)
- iproute2 (for ip; Busybox' ip is very limited)
- tcpdump
- iperf2

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
Signed-off-by: Andreas Braun <andreas.braun@missinglinkelectronics.com>
 2022-04-07 18:41:05 +02:00
Joachim Foerster
5700aba9a0 ZCU106/fpga_zynqmp/ps/petalinux/: dts: Add custom device tree node for mqnic device 
Currently consists of 4 parts:
- Removing stub nodes generated by Xilinx device tree generator.
- Adding a custom, manually edited node (needs manual adjustment in case PS
  settings are changed!)
  NOTE: In the future this node might be reduced or removed all together after
  having added a plugin for Xilinx' device tree generator
  (https://github.com/Xilinx/device-tree-xlnx.git), which properly automatically
  generates such a node.
- Adding eeprom nodes for the SFP module I2C buses.
- Disabling the node for the USER MGT SI570 (U56) chip to make Linux NOT touch
  this chip on startup. See lengthy comment.

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
Signed-off-by: Andreas Braun <andreas.braun@missinglinkelectronics.com>
 2022-04-07 18:41:05 +02:00
Joachim Foerster
2dbea0f913 ZCU106/fpga_zynqmp/ps/petalinux/: Add basic PetaLinux v2021.1 project 
- modify .gitignore compared to generated version by petalinux-create;
  to avoid committing unnecessary files (binaries, toolchain leftovers, ...)
- set machine name to "zcu106-reva"
- disable "copy to tftpboot directory"
- enable FSBL detailed debug output

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
 2022-04-07 17:14:57 +02:00
Joachim Foerster
80d5bda23f ZCU106/fpga_zynqmp: Fix maximum burst length for AXI Master 
Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
 2022-03-31 17:24:16 +02:00
Joachim Foerster
62879ff3ea ZCU106/fpga_zynqmp: Support parameter EVENT_QUEUE_INDEX_WIDTH, reduce Events queues to number of CPU cores 
- Keep parameter defaults in Verilog file at global of 32, though
- Select 4 Event queues via config.tcl, only

Signed-off-by: Andreas Braun <andreas.braun@missinglinkelectronics.com>
Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
 2022-03-31 17:24:16 +02:00
Andreas Braun
dc77c9e92a ZCU106/fpga_zynqmp: Reduce number of IRQs to number of CPU cores 
Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
Signed-off-by: Andreas Braun <andreas.braun@missinglinkelectronics.com>
 2022-03-31 17:22:27 +02:00
Andreas Braun
dce11522fa ZCU106/fpga_zynqmp: Reduce number of RX/TX queues to 32 
Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
 2022-03-31 17:22:27 +02:00
Andreas Braun
35517037e6 ZCU106/: Add design based on ZynqMP PS as host system, Vivado v2021.1 
Signed-off-by: Andreas Braun <andreas.braun@missinglinkelectronics.com>
Signed-off-by: Joachim Förster <joachim.foerster@missinglinkelectronics.com>
 2022-03-31 17:22:27 +02:00