FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-16 08:12:53 +08:00
Code Issues Projects Releases Wiki Activity
2,801 Commits 1 Branch 0 Tags
Commit Graph

2801 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Alex Forencich
01df80df86 fpga/mqnic: Disable MIGs by default 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-12 23:57:27 -07:00
Alex Forencich
6bfaef78bd Properly handle 4KB read requests in UltraScale shim 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-12 21:52:27 -07:00
Alex Forencich
633037d032 Fix direction of config signals 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-12 21:40:08 -07:00
Alex Forencich
5e396ceb87 Rename seg_rc_hdr to seg_rq_hdr 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-12 21:19:48 -07:00
Alex Forencich
5e52a52f5e fpga/mqnic: Add MIGs and HBM controllers for most boards 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-12 19:00:49 -07:00
Alex Forencich
941288e926 fpga/common: Add AXI interfaces for DDR and HBM to core logic and application section 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-12 17:12:23 -07:00
Alex Forencich
eb990643f2 fpga/mqnic: various minor cleanup 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-12 17:12:07 -07:00
Alex Forencich
5f1e74b0e1 Add PROJECT variable, remove multiple stem matches 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-11 13:33:09 -07:00
Alex Forencich
7017e7d49b Explicitly set top module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-11 12:29:01 -07:00
Alex Forencich
ceb6a9ca06 Update clean target 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-11 12:26:39 -07:00
Alex Forencich
9c98f12392 Write debug probes file alongside bit file 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-10 23:37:54 -07:00
Alex Forencich
9628401780 Normalize output file location 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-10 21:47:53 -07:00
Alex Forencich
caf2a0993b fpga: Output hierarchical utilization reports 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-06 21:17:25 -07:00
Alex Forencich
fe37e4a4bb fpga/common: Use correct parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-06 21:15:26 -07:00
Alex Forencich
62711295e0 Update pcie_if model 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-27 15:28:07 -07:00
Alex Forencich
56fe10f27d fpga/common: Fix lost TX request status issue in transmit engine 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-21 15:20:27 -07:00
Alex Forencich
efbeecde35 fpga/common: Clean up parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-21 15:19:49 -07:00
Alex Forencich
ebbddb5559 fpga/common: Add multiple queue test to core testbenches 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-20 21:59:02 -07:00
Alex Forencich
4b8aaea5c1 fpga/common: Add skid buffer to TX/RX engine DMA descriptor outputs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-20 21:50:58 -07:00
Alex Forencich
d1b1e04006 docs: Fix signal names 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-20 21:47:39 -07:00
Alex Forencich
f780008121 Update package versions 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-20 21:42:57 -07:00
Alex Forencich
b9e0af3634 Revert change to early ready conditions for improved throughput 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-18 12:07:11 -07:00
Alex Forencich
fc5964ab90 Update package versions 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-07 20:00:01 -07:00
Alex Forencich
3743b0bcf6 Update package versions 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-07 19:58:22 -07:00
Alex Forencich
1e3dae4767 Update package versions 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-07 19:41:50 -07:00
Alex Forencich
d7904b8007 fpga: Add support for IRQ rate limiting 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-04 15:24:40 -07:00
Alex Forencich
2a69e07acb merged changes in pcie 2022-09-04 12:03:44 -07:00
Alex Forencich
1486da601f fpga: Add clock period parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-04 12:03:35 -07:00
Alex Forencich
916faa0bdd Add IRQ rate limit module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-04 12:02:26 -07:00
Alex Forencich
803841421e fpga/common: Fix tied-off net name 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-03 18:34:42 -07:00
Alex Forencich
d038ba9853 Minor cleanup of MSI-X module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-03 17:19:21 -07:00
Alex Forencich
a1e53e5e46 Fix latch inference 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-03 01:20:39 -07:00
Alex Forencich
fb3fe33d0a Migrate to Zulip 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-01 13:04:33 -07:00
Alex Forencich
44c81574d7 fpga/common: Add backpressure to completion queue manager event/interrupt output 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-16 18:51:53 -07:00
Alex Forencich
647a168299 Enable more peripherals in Zynq designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-16 18:49:02 -07:00
Alex Forencich
1b9f5d1032 fpga/mqnic/ZCU102: Add 10G mqnic design for ZCU102 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-16 01:44:52 -07:00
Alex Forencich
171c2a9a69 fpga/mqnic/ZCU106/fpga_zynqmp: Remove SI570 workaround 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-15 23:54:02 -07:00
Alex Forencich
c5efd8ff0a modules/mqnic: Clean up ring allocation error handling 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-15 23:50:36 -07:00
Alex Forencich
338457cd75 merged changes in pcie 2022-08-15 23:47:49 -07:00
Alex Forencich
a2f07db39f Remove redundant abort signal connection 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-14 14:55:01 -07:00
Alex Forencich
60dd672f6d Move pause signal connection to improve timing 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-14 14:54:27 -07:00
Alex Forencich
edf9b260ab Rename module to match file name 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-14 14:53:15 -07:00
Alex Forencich
4d303ba11b meta-corundum/recipes-devtools/mqnic-tools: Add missing symlink 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-12 13:34:27 -07:00
Alex Forencich
1c1db788ac fpga/common: Fix incorrect parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-08 13:10:05 -07:00
Alex Forencich
693809ab97 modules/mqnic: Use DMA_TO/FROM_DEVICE macros instead of the PCI versions 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-06 01:27:19 -07:00
Alex Forencich
d0ce01de7f fpga/mqnic/S10DX_DK: fix typo 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-05 16:28:15 -07:00
Alex Forencich
6c6648f114 fpga/mqnic: Add RAM inference directive to Intel designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-05 16:27:29 -07:00
Alex Forencich
f3bf63a775 merged changes in pcie 2022-08-05 16:25:42 -07:00
Alex Forencich
d6d59a5675 Don't force DMA RAM into MLABs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-05 16:25:18 -07:00
Alex Forencich
0c877a45fb fpga/build_images.py: update quartus message parsing 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-04 13:40:34 -07:00