Alex Forencich
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0828de78e8
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Add DMA PSDPRAM master model and DMA PSDPRAM testbenches
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-05-28 00:42:47 -07:00 |
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Alex Forencich
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8ad370ac99
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Properly handle PCIE_TAG_COUNT setting of 32 or less
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-05-17 19:12:09 -07:00 |
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Alex Forencich
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2f449d0b29
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Rework write done handling in DMA ram demux module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-05-15 16:44:40 -07:00 |
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Alex Forencich
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4c82a8f465
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Improve status FIFO utilization
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-05-15 01:52:13 -07:00 |
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Alex Forencich
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2d307a6d60
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Add busy status outputs to DMA interface modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-05-12 16:05:44 -07:00 |
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Alex Forencich
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1a4692bf17
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Increase flow control credit threshold for controlling the transmission of posted and non-posted requests in UltraScale shim
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-05-10 14:51:36 -07:00 |
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Alex Forencich
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6591849fe8
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Generate wr_done output based only on wr_cmd_valid, not wr_cmd_be
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-05-10 14:46:47 -07:00 |
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Alex Forencich
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8b392d5127
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Update to latest version of cocotbext-axi
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-05-06 22:37:41 -07:00 |
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Alex Forencich
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1ad973f7a7
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Update ubuntu version in CI
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-02-17 16:05:56 -08:00 |
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Alex Forencich
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c6c83a7c68
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Remove recursively-expanded macros for module parameters in makefiles
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-02-17 15:58:34 -08:00 |
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Alex Forencich
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bc2757dde9
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Cache clock edge events
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-01-31 16:22:05 -08:00 |
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Alex Forencich
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9c5c6e6edf
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Rework parameter handling in example design makefiles
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-01-29 22:56:53 -08:00 |
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Alex Forencich
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5de1bc0df1
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Rework parameter handling in testbench makefiles
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-01-29 22:31:21 -08:00 |
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Alex Forencich
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0c951a4e5a
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Split some long-running tests
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-01-26 21:55:58 -08:00 |
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Alex Forencich
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73728d1994
|
Adjust testbench timeouts
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-01-26 18:47:15 -08:00 |
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Alex Forencich
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28916a56cd
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Update CI configuration
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-01-26 16:41:36 -08:00 |
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Alex Forencich
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6bfaef78bd
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Properly handle 4KB read requests in UltraScale shim
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-10-12 21:52:27 -07:00 |
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Alex Forencich
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633037d032
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Fix direction of config signals
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-10-12 21:40:08 -07:00 |
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Alex Forencich
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5e396ceb87
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Rename seg_rc_hdr to seg_rq_hdr
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-10-12 21:19:48 -07:00 |
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Alex Forencich
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62711295e0
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Update pcie_if model
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-09-27 15:28:07 -07:00 |
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Alex Forencich
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1e3dae4767
|
Update package versions
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-09-07 19:41:50 -07:00 |
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Alex Forencich
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916faa0bdd
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Add IRQ rate limit module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-09-04 12:02:26 -07:00 |
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Alex Forencich
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d038ba9853
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Minor cleanup of MSI-X module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-09-03 17:19:21 -07:00 |
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Alex Forencich
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a1e53e5e46
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Fix latch inference
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-09-03 01:20:39 -07:00 |
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Alex Forencich
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a2f07db39f
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Remove redundant abort signal connection
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-08-14 14:55:01 -07:00 |
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Alex Forencich
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60dd672f6d
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Move pause signal connection to improve timing
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-08-14 14:54:27 -07:00 |
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Alex Forencich
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edf9b260ab
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Rename module to match file name
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-08-14 14:53:15 -07:00 |
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Alex Forencich
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d6d59a5675
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Don't force DMA RAM into MLABs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-08-05 16:25:18 -07:00 |
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Alex Forencich
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91450fcab7
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PCIe flow control is handled in shim; remove flow control from PCIe DMA interface
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-08-03 13:47:02 -07:00 |
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Alex Forencich
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3f3be1e14d
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Implement flow control for P-Tile
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-08-02 22:57:27 -07:00 |
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Alex Forencich
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53ee26f3ec
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Use latest version of cocotbext-pcie
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-08-01 13:25:51 -07:00 |
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Alex Forencich
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7f0bd00170
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Implement flow control for Stratix 10 shim
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-08-01 13:19:01 -07:00 |
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Alex Forencich
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9c434687a8
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Add flow control credit counter to TLP FIFO MUX module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-31 17:35:07 -07:00 |
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Alex Forencich
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ad5a322ee1
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Add PCIe flow control credit count module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-31 17:24:43 -07:00 |
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Alex Forencich
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1dfdd8b0e3
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Timing optimization
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-07-31 17:24:03 -07:00 |
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Alex Forencich
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b1b82a3f2b
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Add pause inputs to TLP mux modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-29 17:16:05 -07:00 |
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Alex Forencich
|
0d9b1d0fb0
|
Implement flow control in UltraScale shim
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-26 14:01:00 -07:00 |
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Alex Forencich
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a5fe40cd42
|
Fix JTAG index
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-22 22:34:26 -07:00 |
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Alex Forencich
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a53509de68
|
Add instance names
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-22 22:34:04 -07:00 |
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Alex Forencich
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90c65dfed7
|
Fix PBA offsets
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-22 22:33:38 -07:00 |
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Alex Forencich
|
5fe904545c
|
Testbench cleanup
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-13 16:35:51 -07:00 |
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Alex Forencich
|
fc90d7f44d
|
Strip version number
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-13 00:40:43 -07:00 |
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Alex Forencich
|
05f51ed05c
|
Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-13 00:32:33 -07:00 |
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Alex Forencich
|
be6bb907c9
|
Register MSI-X control signals
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-13 00:32:19 -07:00 |
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Alex Forencich
|
dbcd211ce1
|
Add example design for DE10-Agilex
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-13 00:31:59 -07:00 |
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Alex Forencich
|
c5382f5e7f
|
Add example design for Stratix 10 DX dev kit
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-13 00:31:39 -07:00 |
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Alex Forencich
|
cf3029364d
|
Add P-Tile example design core module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-13 00:31:13 -07:00 |
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Alex Forencich
|
2a727e04f7
|
Add PCIe interface shim for Intel Stratix 10 DX/Agilex P-Tile
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-12 23:53:34 -07:00 |
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Alex Forencich
|
3f334dbbbb
|
Use MSI-X in example designs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-12 23:32:51 -07:00 |
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Alex Forencich
|
e2588cd995
|
Clean up TCL scripts
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-12 16:23:54 -07:00 |
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