83 Commits

Author	SHA1	Message	Date
Alex Forencich	0830ca6a7a	Add example design for VCU1525	2021-11-18 16:32:38 -08:00
Alex Forencich	fb4b32fba0	Add example design for VCU118	2021-11-18 16:31:55 -08:00
Alex Forencich	cef69d1e1f	Add example design for VCU108	2021-11-18 16:31:18 -08:00
Alex Forencich	6740ddafaf	Add example design for ExaNIC X25	2021-11-18 16:29:52 -08:00
Alex Forencich	0cbe4897da	Add example design for Alveo U50	2021-11-18 16:28:39 -08:00
Alex Forencich	068ea6edc2	Add example design for Alveo U280	2021-11-18 16:27:48 -08:00
Alex Forencich	12fea955d2	Add example design for Alveo U250	2021-11-18 16:26:43 -08:00
Alex Forencich	6e5f9f33f2	Add example design for Alveo U200	2021-11-18 16:25:59 -08:00
Alex Forencich	057edebc36	Add example design for ADM-PCIE-9V3	2021-11-18 16:21:28 -08:00
Alex Forencich	9632a40ad7	Parameter cleanup	2021-11-18 14:23:47 -08:00
Alex Forencich	667076ee39	Testbench cleanup	2021-11-18 13:50:32 -08:00
Alex Forencich	a330c6e7f0	Testbench cleanup	2021-11-18 13:45:55 -08:00
Alex Forencich	419ee057c8	Fix instance name	2021-11-18 13:44:46 -08:00
Alex Forencich	6920845989	Update example design testbenches	2021-11-17 17:21:57 -08:00
Alex Forencich	5b528158df	Remove deprecated assignments	2021-11-09 11:55:12 -08:00
Alex Forencich	9883e776c3	Parameter cleanup	2021-11-03 20:46:40 -07:00
Alex Forencich	e31345071d	Add AXI RAM for example designs	2021-11-03 19:12:55 -07:00
Alex Forencich	f4ffdb727d	Add example design for BittWare 520N-MX	2021-11-03 18:13:40 -07:00
Alex Forencich	f2fad37273	Add example design for Stratix 10 MX development kit	2021-11-03 18:12:17 -07:00
Alex Forencich	9297c518f1	Add example design for ExaNIC X10	2021-11-03 18:10:17 -07:00
Alex Forencich	d43067a805	Add example design for fb2CG@KU15P	2021-11-03 18:09:46 -07:00
Alex Forencich	84009500a8	Add example design core logic modules	2021-11-03 01:51:10 -07:00
Alex Forencich	47a2570647	Set class code to memory controller, set subsystem ID based on board	2021-11-02 14:39:33 -07:00
Alex Forencich	ad157ca3ad	Enable interrupts	2021-11-02 14:35:42 -07:00
Alex Forencich	38358ffa43	Print subsystem IDs	2021-11-02 14:35:25 -07:00
Alex Forencich	545eca653c	Fix kernel module coding style	2021-10-22 14:36:41 -07:00
Alex Forencich	90959b8795	Add default_nettype none and resetall directives	2021-10-20 17:49:30 -07:00
Alex Forencich	b7e8ca1311	Fix kernel module coding style	2021-10-13 16:51:32 -07:00
Alex Forencich	75905778bc	Use DRIVER_NAME define	2021-10-01 23:44:50 -07:00
Alex Forencich	437c69abc4	Call remove from shutdown	2021-10-01 18:25:31 -07:00
Alex Forencich	93aed3ede9	Remove UltraScale specific counters	2021-10-01 18:25:12 -07:00
Alex Forencich	4b59bad937	Print more PCIe information	2021-10-01 17:38:58 -07:00
Alex Forencich	cb52a82498	Remove MODULE_SUPPORTED_DEVICE, which was never implemented and was removed in kernel version 5.12	2021-10-01 17:35:43 -07:00
Alex Forencich	d97ac3105f	Convert VCU118 to x16	2021-10-01 15:56:28 -07:00
Alex Forencich	618fdff0b8	Convert ADM_PCIE_9V3 to x16	2021-10-01 15:21:10 -07:00
Alex Forencich	a7b669e22f	Update makefiles	2021-10-01 02:39:15 -07:00
Alex Forencich	14c84088ee	Reorganize driver code	2021-08-13 14:22:32 -07:00
Alex Forencich	e4508b242f	Update example designs	2021-08-02 18:36:25 -07:00
Alex Forencich	ccc44d7dbb	Use 64 bit BARs in example designs	2021-06-16 23:23:53 -07:00
Alex Forencich	a79027fdd1	Remove DEV_BAR_CNT define	2021-06-16 21:36:34 -07:00
Alex Forencich	bdfeaa84ca	Update testbenches	2021-03-06 20:06:23 -08:00
Alex Forencich	266fed8d20	Update example design file list	2021-02-28 19:35:35 -08:00
Alex Forencich	062495b780	Remove redundant parameter PCIE_EXT_TAG_ENABLE	2021-02-25 18:20:08 -08:00
Alex Forencich	8294eecd65	Remove redundant parameter PCIE_TAG_WIDTH	2021-02-25 18:10:59 -08:00
Alex Forencich	633b47ef7f	Update XDC files	2021-02-06 17:14:26 -08:00
Alex Forencich	87a6efe05c	Rework sim_build output directory, fix default makefile target	2020-12-29 16:26:48 -08:00
Alex Forencich	cabad17552	Migrate example design testbenches to cocotb	2020-12-18 22:10:32 -08:00
Alex Forencich	5546e40812	Fix user_clk_frequency setting in testbenches	2020-10-12 23:05:28 -07:00
Alex Forencich	d22d3e8bd1	Update VCU118 XDC	2020-10-06 00:40:16 -07:00
Alex Forencich	8f8cb39157	Update flash programming configuration for ExaNIC X10 and X25	2020-10-03 15:26:56 -07:00