169 Commits

Author	SHA1	Message	Date
minseongg	dc5c8232f9	Add cmac_pad testbench	2021-06-28 22:33:57 -07:00
Alex Forencich	0a7f1ccbbe	Remove string parameters	2021-06-02 18:18:23 -07:00
Alex Forencich	15cb21dbd1	Reorganize timing constraints	2021-05-20 15:24:01 -07:00
Alex Forencich	32abea89fa	Update testbenches	2021-03-06 20:30:25 -08:00
Alex Forencich	a3c104f7dd	Connect write done signals	2021-02-24 15:07:26 -08:00
Alex Forencich	c0c2f933c0	Rework sim_build output directory, fix default makefile target	2020-12-29 17:28:53 -08:00
Alex Forencich	0c0fdc479b	Update testbenches for async send/recv	2020-12-18 17:40:36 -08:00
Alex Forencich	b5ee772761	Migrate test infrastructure to cocotb	2020-12-15 16:52:20 -08:00
Alex Forencich	3003b3228d	Fix backpressure bug in TX checksum module	2020-12-12 21:51:54 -08:00
Alex Forencich	91edbbf3dc	Rename port and interface modules	2020-11-26 15:05:59 -08:00
Alex Forencich	0d1617c05c	Update DMA RAM instances	2020-09-25 21:51:31 -07:00
Alex Forencich	a37d9b3465	New transceiver control reigster definitions	2020-09-19 17:25:58 -07:00
Alex Forencich	3284ec3848	New I2C register definitions	2020-09-19 17:25:58 -07:00
Alex Forencich	cbaffeeac7	Limit RX DMA size to configured MTU size	2020-08-25 18:48:17 -07:00
Alex Forencich	495178e1dc	Fix mask	2020-07-28 18:30:52 -07:00
Alex Forencich	4e958096b2	Update driver model to set MTU registers	2020-05-01 19:19:56 -07:00
Alex Forencich	ae775a9386	Rewrite RX buffer management	2020-05-01 19:00:58 -07:00
Alex Forencich	8b535e54ac	Add MTU registers	2020-05-01 18:55:01 -07:00
Alex Forencich	ca0cbf4d93	Update parameters	2020-05-01 17:22:21 -07:00
Alex Forencich	1f76606667	Move TDMA registers	2020-05-01 16:55:57 -07:00
Alex Forencich	ded213460d	Rewrite TX buffer management	2020-05-01 14:29:52 -07:00
Alex Forencich	1c7b7937e5	Limit in-flight descriptor requests in TX engine	2020-04-30 23:37:41 -07:00
Alex Forencich	45ec6657b1	Limit in-flight descriptor requests in RX engine	2020-04-30 23:29:43 -07:00
Alex Forencich	31cec8d0c1	Fix cmac_pad frame truncation bug	2020-04-22 23:23:34 -07:00
Alex Forencich	9e64d19ea5	Use scatter descriptor blocks in driver model	2020-04-21 01:04:07 -07:00
Alex Forencich	2c6e9673f7	Add log_desc_block_size ring parameter in driver model	2020-04-21 00:58:12 -07:00
Alex Forencich	e14cfa0a58	Update port and interface modules	2020-04-20 21:25:21 -07:00
Alex Forencich	7087a595e9	Update RX and TX engines to support descriptor blocks	2020-04-20 21:24:25 -07:00
Alex Forencich	0fb60d718d	Add log desc block size to desc_fetch module	2020-04-20 21:01:55 -07:00
Alex Forencich	d0cf549057	Add log desc block size field to queue manager	2020-04-20 20:45:10 -07:00
Alex Forencich	50af74aa88	Change QUEUE_LOG_SIZE_WIDTH to LOG_QUEUE_SIZE_WIDTH	2020-04-20 18:43:26 -07:00
Alex Forencich	a196cd227c	Enable bus mastering and MSI in driver model	2020-03-12 15:32:08 -07:00
Alex Forencich	457f4d7f3f	Use configured ring stride	2020-03-12 15:28:00 -07:00
Alex Forencich	0c32192226	Use constants instead of magic numbers	2020-03-12 15:08:20 -07:00
Alex Forencich	1216f7a76e	Offset packet start by 10 bytes to match Linux kernel skb alignment	2020-03-08 21:56:08 -07:00
Alex Forencich	23aef37aff	Rewrite resets	2020-03-08 16:56:06 -07:00
Alex Forencich	248a0b4f93	Convert descriptor to DMA operation without storing in table	2020-03-08 00:22:55 -08:00
Alex Forencich	f7a1a7ef95	Add descriptor FIFOs	2020-03-07 22:28:59 -08:00
Alex Forencich	4dd5104f4d	Stripe completion queues across event queues	2020-03-06 00:58:30 -08:00
Alex Forencich	627153cd9b	Fix signal sizing bug	2020-03-06 00:24:13 -08:00
Alex Forencich	2b14ab2555	Update cmac_pad to pad frames to 60 bytes	2020-02-26 13:36:19 -08:00
Alex Forencich	217217b45e	Remove unused table fields	2019-12-30 22:02:22 -08:00
Alex Forencich	f642bb7f7e	Reserve packet data slot early and release on dequeue fail	2019-12-30 17:49:42 -08:00
Alex Forencich	3690fdeb7d	Pull out pipeline parameters	2019-12-28 01:16:16 -08:00
Alex Forencich	58200e9851	Fix testbench	2019-12-28 01:15:40 -08:00
Alex Forencich	db9e1df1fa	Update pipelining to enable URAM inference	2019-12-28 01:13:57 -08:00
Alex Forencich	f97ff4407b	Change driver model max packet size	2019-12-23 14:41:52 -08:00
Alex Forencich	cbde1abaf9	Add CMAC pad module	2019-12-23 14:40:51 -08:00
Alex Forencich	45a33b8293	Fix scheduler bug	2019-12-16 14:13:01 -08:00
Alex Forencich	7a68abbb84	Split control and data descriptor paths to DMA engine	2019-12-13 14:15:25 -08:00