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3,031 Commits 1 Branch 0 Tags
Commit Graph

843 Commits

Author SHA1 Message Date
Alex Forencich
217217b45e Remove unused table fields 2019-12-30 22:02:22 -08:00
Alex Forencich
f642bb7f7e Reserve packet data slot early and release on dequeue fail 2019-12-30 17:49:42 -08:00
Alex Forencich
a501f33c09 Update parameters 2019-12-29 16:46:25 -08:00
Alex Forencich
0955a4101f Fix signal widths 2019-12-29 16:45:32 -08:00
Alex Forencich
3690fdeb7d Pull out pipeline parameters 2019-12-28 01:16:16 -08:00
Alex Forencich
58200e9851 Fix testbench 2019-12-28 01:15:40 -08:00
Alex Forencich
db9e1df1fa Update pipelining to enable URAM inference 2019-12-28 01:13:57 -08:00
Alex Forencich
f97ff4407b Change driver model max packet size 2019-12-23 14:41:52 -08:00
Alex Forencich
cbde1abaf9 Add CMAC pad module 2019-12-23 14:40:51 -08:00
Alex Forencich
96bb5feead merged changes in pcie 2019-12-23 14:39:18 -08:00
Alex Forencich
45a33b8293 Fix scheduler bug 2019-12-16 14:13:01 -08:00
Alex Forencich
7a68abbb84 Split control and data descriptor paths to DMA engine 2019-12-13 14:15:25 -08:00
Alex Forencich
88e31d0ccb Connect PCIe credit interface to DMA cores 2019-12-13 12:41:50 -08:00
Alex Forencich
59d39ca7ec merged changes in pcie 2019-12-07 18:53:55 -08:00
Alex Forencich
4dafedca27 Reschedule queue if necessary 2019-12-06 14:21:20 -08:00
Alex Forencich
6270278c75 Add RSS support 2019-12-06 14:15:16 -08:00
Alex Forencich
b5d7bd15b4 Add rx_hash module and testbenches 2019-12-05 13:47:07 -08:00
Alex Forencich
0e7a91d927 Connect RQ sequence number 2019-12-03 18:19:17 -08:00
Alex Forencich
936cfd9524 merged changes in pcie 2019-12-03 15:48:38 -08:00
Alex Forencich
317aa34db5 Expose control bits 2019-11-21 15:12:49 -08:00
Alex Forencich
463f2053b0 Add port register port_mtu 2019-11-18 16:30:32 -08:00
Alex Forencich
03465b4b25 Fix parameter 2019-11-18 16:27:02 -08:00
Alex Forencich
489506e4c0 Add FPGA ID register 2019-11-17 12:46:27 -08:00
Alex Forencich
445f80e6f2 Connect QSPI flash on Alpha Data board 2019-11-17 01:01:52 -08:00
Alex Forencich
33be402b16 Update widths 2019-11-14 00:02:10 -08:00
Alex Forencich
bce2756c0c Parametrize checksum offload 2019-11-13 23:49:50 -08:00
Alex Forencich
f36773660d Set flash ID 2019-11-06 15:05:32 -08:00
Alex Forencich
c954b55da9 Remove tx_scheduler_tdma_rr module 2019-11-05 22:10:47 -08:00
Alex Forencich
3655a6df00 Use new TDMA scheduler control module 2019-11-05 22:09:51 -08:00
Alex Forencich
93de8a1b32 Remove extraneous init code 2019-11-05 18:32:36 -08:00
Alex Forencich
e43c011e33 Update testbenches 2019-11-05 18:31:41 -08:00
Alex Forencich
7fb022abe1 Add tx_scheduler_ctrl_tdma module 2019-11-05 18:24:22 -08:00
Alex Forencich
f53a6b20e8 Add timeslot count to port registers 2019-11-05 16:59:40 -08:00
Alex Forencich
f65b139797 Add scheduler control input to tx_scheduler_rr 2019-11-05 16:56:10 -08:00
Alex Forencich
304e0b7410 Update TDMA scheduler to generate status signals and avoid producing runt outputs 2019-11-05 16:55:19 -08:00
Alex Forencich
e92485a41e Fix register definitions 2019-11-05 16:44:57 -08:00
Alex Forencich
cc592b44d7 Use correct PCIe core model 2019-11-04 14:13:12 -08:00
Alex Forencich
381fd871c5 Parametrize tag widths 2019-10-31 23:25:34 -07:00
Alex Forencich
736321641f Parametrize addressing 2019-10-31 23:24:42 -07:00
Alex Forencich
d97407f245 merged changes in axi 2019-10-31 14:46:25 -07:00
Alex Forencich
f43cd09dac Add ExaNIC X25 mqnic design 2019-10-30 17:43:33 -07:00
Alex Forencich
533f19dfb7 merged changes in eth 2019-10-24 12:13:08 -07:00
Alex Forencich
407c2a3a62 merged changes in pcie 2019-10-22 16:07:47 -07:00
Alex Forencich
415c2b36be Remove old code 2019-10-19 00:38:52 -07:00
Alex Forencich
6473786a4c Add 25G mqnic design for Alpha Data board 2019-10-18 03:26:46 -07:00
Alex Forencich
02cc2c7377 Use PCIe gen 3 x16 2019-10-17 19:02:46 -07:00
Alex Forencich
1a06f16130 Update VCU118 XDC file 2019-10-17 16:07:42 -07:00
Alex Forencich
8fa7e40507 Use new DMA subsystem 2019-10-17 16:02:14 -07:00
Alex Forencich
16c5eee499 merged changes in pcie 2019-10-17 11:46:24 -07:00
Alex Forencich
9ab0d50c0a Add PCIe interface tuser width parameters 2019-10-05 13:56:24 -07:00