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Code Issues Projects Releases Wiki Activity
3,031 Commits 1 Branch 0 Tags
Commit Graph

843 Commits

Author SHA1 Message Date
Alex Forencich
089a46c811 Add VCU118 mqnic design 2019-07-25 20:21:11 -07:00
Alex Forencich
5b8898f2bc Add VCU108 mqnic_tdma design 2019-07-25 17:44:13 -07:00
Alex Forencich
958aec8e8c Add VCU108 mqnic design 2019-07-25 17:05:56 -07:00
Alex Forencich
90900f144a merged changes in axi 2019-07-24 18:19:15 -07:00
Alex Forencich
e809912456 merged changes in eth 2019-07-24 18:02:17 -07:00
Alex Forencich
db297ce725 merged changes in pcie 2019-07-24 18:02:14 -07:00
Alex Forencich
574aeeef63 merged changes in axi 2019-07-24 18:02:10 -07:00
Alex Forencich
0a16bb1299 Fix parametrization 2019-07-24 01:45:18 -07:00
Alex Forencich
a6c4b8b1b7 Change board IDs 2019-07-21 15:27:01 -07:00
Alex Forencich
ea7ccd182e Move MAC out of port module 2019-07-19 23:29:03 -07:00
Alex Forencich
1917ed3912 merged changes in eth 2019-07-19 18:17:57 -07:00
Alex Forencich
9de2101cdc Update ExaNIC X10 testbenches 2019-07-19 18:01:24 -07:00
Alex Forencich
eb92578699 Update FIFO instances 2019-07-19 16:17:36 -07:00
Alex Forencich
00ebe73bdc merged changes in eth 2019-07-19 15:52:41 -07:00
Alex Forencich
5b15f03f69 Add ADM-PCIE-9V3 mqnic_tdma design 2019-07-19 15:43:40 -07:00
Alex Forencich
a9179dc550 Add ExaNIC X10 mqnic_tdma design 2019-07-19 15:42:18 -07:00
Alex Forencich
4b37a4484d Add TDMA round-robin scheduler 2019-07-19 15:40:53 -07:00
Alex Forencich
750112ff06 Add ADM-PCIE-9V3 mqnic design 2019-07-19 15:39:40 -07:00
Alex Forencich
4c3f2412df Add TDMA BERT modules and testbenches 2019-07-19 15:28:57 -07:00
Alex Forencich
1df012a8d4 Add ExaNIC X10 design 2019-07-17 16:57:04 -07:00
Alex Forencich
fcd8b1b8e9 Add driver simulation model 2019-07-17 16:46:12 -07:00
Alex Forencich
ce011453d6 Add interface module 2019-07-17 16:43:12 -07:00
Alex Forencich
351404813a Add port module 2019-07-17 16:42:39 -07:00
Alex Forencich
65f0ff28b5 Add Ethernet interface module 2019-07-17 16:41:21 -07:00
Alex Forencich
12f215fe26 Add round robin transmit scheduler 2019-07-17 16:40:35 -07:00
Alex Forencich
bda4e87371 Add event management modules 2019-07-17 16:39:59 -07:00
Alex Forencich
f94e83e520 Add transmit and receive engines 2019-07-17 16:38:57 -07:00
Alex Forencich
6100e3ad78 Add RX checksum module and testbench 2019-07-16 00:42:49 -07:00
Alex Forencich
755c7959be merged changes in eth 2019-07-16 00:40:02 -07:00
Alex Forencich
a653f2d839 Add TDMA scheduler module and testbench 2019-07-16 00:19:22 -07:00
Alex Forencich
fc9a6c1c50 Add completion queue manager module and testbench 2019-07-16 00:16:07 -07:00
Alex Forencich
46f653f097 Add queue manager module and testbench 2019-07-16 00:15:50 -07:00
Alex Forencich
3d4ba0fa3f Add testbench symlinks 2019-07-16 00:15:25 -07:00
Alex Forencich
ce709ed4c0 merged changes in pcie 2019-07-15 20:39:17 -07:00
Alex Forencich
c83b04f9db merged changes in eth 2019-07-15 18:09:52 -07:00
Alex Forencich
16262b2ead merged changes in pcie 2019-07-15 17:25:16 -07:00
Alex Forencich
debcdb58ad merged changes in eth 2019-07-15 16:43:21 -07:00
Alex Forencich
a9f3cf001d merged changes in eth 2019-07-15 16:17:07 -07:00
Alex Forencich
dcea219303 added pcie as a subproject 
git-subtree-dir: fpga/lib/pcie
git-subtree-mainline: 5ad725bd0ff04fe7fe7ab9983c0c3e64355e0dd2
git-subtree-split: 1d79a4375b42a8dad274b3e0a757f833400d556e
 2019-07-15 14:55:57 -07:00
Alex Forencich
5ad725bd0f added axi as a subproject 
git-subtree-dir: fpga/lib/axi
git-subtree-mainline: d644d8c5e30c9b704704d8974ee73f1573ac2af2
git-subtree-split: 23a14dc5dfa1d18c0c1e73ff00bf462d1b7ea5da
 2019-07-15 14:55:51 -07:00
Alex Forencich
d644d8c5e3 Add axis symlink 2019-07-15 14:55:44 -07:00
Alex Forencich
de181120b8 added eth as a subproject 
git-subtree-dir: fpga/lib/eth
git-subtree-mainline: 4cdce8caa74728a4973261dae0e00fcd479af9ac
git-subtree-split: e5171d874916b3e23a02d5621e91dd9ff02b7fcb
 2019-07-15 14:55:25 -07:00
Alex Forencich
4cdce8caa7 Add subtree scripts 2019-07-15 14:55:10 -07:00