Alex Forencich
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c6c83a7c68
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Remove recursively-expanded macros for module parameters in makefiles
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-02-17 15:58:34 -08:00 |
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Alex Forencich
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5de1bc0df1
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Rework parameter handling in testbench makefiles
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-01-29 22:31:21 -08:00 |
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Alex Forencich
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0d9b1d0fb0
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Implement flow control in UltraScale shim
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-07-26 14:01:00 -07:00 |
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Alex Forencich
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19b1af0388
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Update Xilinx UltraScale shims to support TLP straddling
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-07-04 00:46:07 -07:00 |
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Alex Forencich
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70dc92c24e
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Rework TLP interface parametrization
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-06-05 13:27:04 -07:00 |
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Alex Forencich
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ee59fc10e0
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Update testbenches for new version of cocotbext-pcie
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-06-05 13:26:27 -07:00 |
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Alex Forencich
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5208b2844c
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Add MSI-X support to shims
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-06-02 23:35:34 -07:00 |
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Alex Forencich
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ba5188dd93
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Update testbenches for new version of cocotbext-pcie
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-06-02 23:33:52 -07:00 |
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Alex Forencich
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2c3a5f4bda
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Update testbenches
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2021-11-17 17:21:35 -08:00 |
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Alex Forencich
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5b528158df
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Remove deprecated assignments
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2021-11-09 11:55:12 -08:00 |
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Alex Forencich
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7810b3c99e
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Connect RQ sequence number ports in pcie_us_if testbench
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2021-08-11 19:53:28 -07:00 |
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Alex Forencich
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ac96ae97d3
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Add flow control signals to pcie_us_if
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2021-08-11 19:37:51 -07:00 |
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Alex Forencich
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836d14bad6
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Add PCIe interface shim for Xilinx UltraScale
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2021-08-04 01:03:31 -07:00 |
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