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7 Commits

Author SHA1 Message Date
Alex Forencich
edd1d546d5 Fix 256-bit RC interface framing 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-06 23:14:19 -07:00
Alex Forencich
19b1af0388 Update Xilinx UltraScale shims to support TLP straddling 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-04 00:46:07 -07:00
Alex Forencich
33e21a6f9b Remove extraneous parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-11 01:09:06 -07:00
Alex Forencich
27f749d5a5 Add strobe outputs to shims 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-07 14:23:24 -07:00
Alex Forencich
70dc92c24e Rework TLP interface parametrization 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-05 13:27:04 -07:00
Alex Forencich
90959b8795 Add default_nettype none and resetall directives 2021-10-20 17:49:30 -07:00
Alex Forencich
836d14bad6 Add PCIe interface shim for Xilinx UltraScale 2021-08-04 01:03:31 -07:00