201 Commits

Author	SHA1	Message	Date
Alex Forencich	4c8fcef230	Add RQ sequence number inputs, TX_LIMIT parameter to ultrascale read DMA modules	2019-11-26 16:30:30 -08:00
Alex Forencich	c5a0d05b47	Add OP_TABLE_SIZE parameter to testbenches	2019-11-26 00:00:49 -08:00
Alex Forencich	e7bd0a62f1	Implement RQ sequence numbers in Ultrascale models	2019-11-25 18:07:49 -08:00
Alex Forencich	bbcdcc17bc	Rename OP_TAG_WIDTH to OP_TABLE_SIZE	2019-11-25 14:59:53 -08:00
Alex Forencich	176e1159a3	Update python parameter computation to match verilog clog2	2019-11-24 00:01:33 -08:00
Alex Forencich	f6f8e556ef	Update tag parameters	2019-11-23 21:18:46 -08:00
Alex Forencich	6c6e3c8212	Remove extraneous parameter connections	2019-11-23 21:15:33 -08:00
Alex Forencich	b2c5004962	Fix discontinue masks	2019-11-23 00:20:21 -08:00
Alex Forencich	52c502227f	Remove unused client tag ports and parameters	2019-11-15 00:55:13 -08:00
Alex Forencich	34c97150e8	Fix get_free_tag	2019-11-04 14:11:24 -08:00
Alex Forencich	3a791afd37	Update DMA interface modules to support 512 bit interface	2019-10-14 16:23:18 -07:00
Alex Forencich	553d7e05fe	Update AXI DMA modules to support 512 bit interface	2019-10-14 16:22:09 -07:00
Alex Forencich	f8bc6c31e5	Update AXI master modules to support 512 bit interface	2019-10-14 16:20:46 -07:00
Alex Forencich	af09059248	Update AXI lite master module to support 512 bit interface	2019-10-14 15:58:38 -07:00
Alex Forencich	39200d84cb	Update simulation models to support 512 bit interface	2019-10-14 15:45:41 -07:00
Alex Forencich	2c43a6e189	Use mmap objects instead of bytearrays	2019-10-13 15:41:12 -07:00
Alex Forencich	fdd7faef4f	Add Xilinx Ultrascale PCIe DMA interface modules and testbenches	2019-10-12 23:03:42 -07:00
Alex Forencich	e1035ed57d	Add AXI stream sink DMA client module and testbench	2019-10-12 22:35:57 -07:00
Alex Forencich	baeeb8ea5c	Add AXI stream source DMA client module and testbench	2019-10-12 22:34:15 -07:00
Alex Forencich	5e9254d519	Check is_eof_0 in RCSink	2019-10-12 18:58:27 -07:00
Alex Forencich	9b5a5db4d1	Add USPcieFrame intermediate format	2019-10-12 18:01:39 -07:00
Alex Forencich	603a6e18e2	Fix RC channel sideband byte enables	2019-10-11 14:16:44 -07:00
Alex Forencich	b7a505acfd	Add segmented DMA RAM simulation model	2019-10-08 15:14:32 -07:00
Alex Forencich	295b6a507e	Use constants instead of magic numbers	2019-10-01 17:30:09 -07:00
Alex Forencich	3817736aa1	Use constants instead of magic numbers	2019-10-01 17:24:18 -07:00
Alex Forencich	1b91200a4a	Implement error code	2019-10-01 17:17:42 -07:00
Alex Forencich	b2d9a6a77f	Add constants	2019-10-01 17:15:15 -07:00
Alex Forencich	836246ec4d	Add missing asserts	2019-09-29 12:55:53 -07:00
Alex Forencich	e97e4ad423	Parametrize tuser signal widths	2019-09-26 23:30:03 -07:00
Alex Forencich	49f9524aeb	Update testbenches	2019-09-17 21:46:54 -07:00
Alex Forencich	e3ad96ef07	Add RQ channel passthrough to pcie_us_axi_dma_wr to eliminiate external mux	2019-09-17 16:32:47 -07:00
Alex Forencich	6e5a3934b2	Add get_free_tag methods	2019-07-15 20:38:09 -07:00
Alex Forencich	4bf1205514	Fix completion handling in function	2019-07-15 20:25:23 -07:00
Alex Forencich	f1348db2f7	Add Ultrascale Plus PCIe hard IP core model and testbench	2019-07-15 17:18:39 -07:00
Alex Forencich	d3b24e734f	Don't use traceSignals	2019-07-14 21:45:10 -07:00
Alex Forencich	209cb7d41d	Fix completion handling	2019-06-12 21:29:19 -07:00
Alex Forencich	6810c75723	Fix parameter	2019-05-09 23:20:36 -07:00
Alex Forencich	2f09c69e34	Add wrappers for word access	2019-04-22 16:43:21 -07:00
Alex Forencich	56ebc966e1	Update parameters	2019-03-03 13:37:34 -08:00
Alex Forencich	33dceb493b	More asserts	2019-03-01 01:09:27 -08:00
Alex Forencich	67d31ecef0	Set more parameters during enumeration	2019-03-01 01:07:57 -08:00
Alex Forencich	f92c1ea980	Reorder capability registrations	2019-02-28 23:46:39 -08:00
Alex Forencich	1480be2173	Rewrite capability management	2019-02-28 23:45:23 -08:00
Alex Forencich	6baede4717	Broadcast message support	2019-02-15 18:04:46 -08:00
Alex Forencich	1630200cd8	Implement proper downstream TLP routing	2019-02-15 17:55:24 -08:00
Alex Forencich	178133498b	Fix indentation	2019-02-15 17:23:33 -08:00
Alex Forencich	13d35569fa	Match IO bars for routing IO operations	2019-02-15 17:23:14 -08:00
Alex Forencich	35a4d62fb8	Split SwitchBridge into separate upstream and downstream ports	2019-02-15 16:56:21 -08:00
Alex Forencich	247bca01f3	Add default_switch_port parameter	2019-02-15 15:26:09 -08:00
Alex Forencich	8cb607be04	Fix calls to read and write root complex regions	2019-02-15 14:40:24 -08:00