77 Commits

Author	SHA1	Message	Date
Alex Forencich	0e15a7a16b	Avoid critical warning from placement constraints when configured with a single interface	2022-03-17 15:39:13 -07:00
Alex Forencich	059d9b5e37	Add Ethernet interface placement constraints for AU200	2022-03-17 00:51:05 -07:00
Alex Forencich	25421b8994	Update placement constraints	2022-03-15 15:28:43 -07:00
Alex Forencich	74be2d9b57	Unified 10G/25G design for AU200	2022-03-14 21:38:31 -07:00
Alex Forencich	8168469ec8	Update config.tcl	2022-03-14 14:45:38 -07:00
Alex Forencich	d9e79c9923	Rename cores to match transceiver type	2022-03-03 22:41:34 -08:00
Alex Forencich	f8950897bc	Update AU200 to use new wrapper	2022-03-03 17:34:42 -08:00
Alex Forencich	2909d205de	Remove unused files	2022-02-16 17:40:28 -08:00
Alex Forencich	3997e0d95b	Parametriztion updates, add RAM_ADDR_WIDTH as a top-level parameter	2022-02-15 18:01:43 -08:00
Alex Forencich	c98258bf05	Fix parametrization	2022-02-13 23:19:09 -08:00
Alex Forencich	627ac359d5	Add layer 2 ingress/egress modules	2022-02-13 23:09:41 -08:00
Alex Forencich	b7bc240aa6	Add JTAG and GPIO passthroughs to application section	2022-01-27 23:06:05 -08:00
Alex Forencich	aab30c8cd0	Add transceiver quad wrappers	2022-01-16 18:28:22 -08:00
Alex Forencich	335a5e890b	Initial implementation of shared interface datapath	2021-12-31 14:33:31 -08:00
Alex Forencich	ce21774f06	Register space reorganization	2021-12-29 22:31:46 -08:00
Alex Forencich	8548e8570f	Update vivado.mk	2021-12-20 22:03:06 -08:00
Alex Forencich	7a43618e3c	Use start_soon instead of fork	2021-12-10 20:43:21 -08:00
Alex Forencich	bc8a8cdc58	Update 100G designs to use correct clock for PTP RX timestamps	2021-11-19 01:54:58 -08:00
Alex Forencich	886111c9e6	Update 10G designs for PTP separate RX clock	2021-11-19 01:52:23 -08:00
Alex Forencich	af3b6312a9	Add PTP_USE_SAMPLE_CLOCK parameter to testbenches	2021-11-18 21:12:06 -08:00
Alex Forencich	5bf9de656c	Update testbenches	2021-11-17 18:08:40 -08:00
Alex Forencich	38c85a6bcd	Set subsystem ID based on board, remove unnecessary configuration settings	2021-11-02 15:32:55 -07:00
Alex Forencich	6a7a91856f	Rework GT instances in Alveo U200 10G design	2021-10-21 19:58:22 -07:00
Alex Forencich	7ac4797336	Add default_nettype none and resetall directives	2021-10-20 21:53:39 -07:00
Alex Forencich	607257d7bb	Fix connections	2021-10-20 20:43:11 -07:00
Alex Forencich	982edfeda7	Update file lists	2021-10-20 19:37:37 -07:00
Alex Forencich	39fbc194fd	Update makefiles	2021-09-20 18:22:47 -07:00
Alex Forencich	d7e9e91644	Fix FIFO size parameter defaults	2021-09-11 17:42:24 -07:00
Alex Forencich	ed418f101a	Update Alveo U200 designs	2021-09-10 23:40:53 -07:00
Alex Forencich	bd3fa6abfd	Update vivado.mk	2021-08-31 20:03:33 -07:00
Alex Forencich	d46cb16dbf	Add scheduler block	2021-08-30 01:28:55 -07:00
Alex Forencich	f71d28c6d8	Normalize RAM size and max frame size	2021-08-20 21:18:44 -07:00
Alex Forencich	34150323df	Remove obsolete packet table size parameters	2021-08-20 18:15:06 -07:00
Alex Forencich	84e19ca305	Update file lists	2021-08-16 18:12:19 -07:00
Alex Forencich	38f766646b	Connect flow control signals to pcie_us_if	2021-08-12 00:05:43 -07:00
Alex Forencich	6517d43ee7	Add missing connection	2021-08-11 23:52:44 -07:00
Alex Forencich	a19474f9dd	Use AXI lite crossbar	2021-08-11 01:31:34 -07:00
Alex Forencich	3e489fde27	Fix instance name	2021-08-04 12:37:13 -07:00
Alex Forencich	0b65a1271a	Use new PCIe DMA modules	2021-08-04 01:20:57 -07:00
Alex Forencich	e0e34a9f0d	Update designs for PCIe module changes	2021-08-02 23:04:52 -07:00
Alex Forencich	4ed99c6f87	Remove CMS IP version number	2021-07-03 00:09:10 -07:00
Alex Forencich	0a7f1ccbbe	Remove string parameters	2021-06-02 18:18:23 -07:00
Alex Forencich	15cb21dbd1	Reorganize timing constraints	2021-05-20 15:24:01 -07:00
Alex Forencich	7b2a0a1aed	Update testbenches	2021-04-28 20:54:44 -07:00
Alex Forencich	77bb4b9dd8	Add PTP support at 100G on Alveo U200	2021-04-01 16:52:00 -07:00
Alex Forencich	1aeeb0bbe2	Update designs for PTP CDC and Ethernet MAC module changes	2021-03-30 16:41:31 -07:00
Alex Forencich	32abea89fa	Update testbenches	2021-03-06 20:30:25 -08:00
Alex Forencich	d416e9f7fa	Roll back PCIe tag count to 64	2021-03-05 14:04:52 -08:00
Alex Forencich	a644d6dd3f	Update Vivado makefiles	2021-03-01 23:05:37 -08:00
Alex Forencich	d0b19efce5	Reconcile PCIe changes	2021-03-01 00:25:15 -08:00