23 Commits

Author	SHA1	Message	Date
Alex Forencich	0e7a91d927	Connect RQ sequence number	2019-12-03 18:19:17 -08:00
Alex Forencich	489506e4c0	Add FPGA ID register	2019-11-17 12:46:27 -08:00
Alex Forencich	33be402b16	Update widths	2019-11-14 00:02:10 -08:00
Alex Forencich	f36773660d	Set flash ID	2019-11-06 15:05:32 -08:00
Alex Forencich	93de8a1b32	Remove extraneous init code	2019-11-05 18:32:36 -08:00
Alex Forencich	e43c011e33	Update testbenches	2019-11-05 18:31:41 -08:00
Alex Forencich	736321641f	Parametrize addressing	2019-10-31 23:24:42 -07:00
Alex Forencich	8fa7e40507	Use new DMA subsystem	2019-10-17 16:02:14 -07:00
Alex Forencich	9ab0d50c0a	Add PCIe interface tuser width parameters	2019-10-05 13:56:24 -07:00
Alex Forencich	9a1a58f608	Add PCIe interface tuser width parameters	2019-10-04 16:51:07 -07:00
Alex Forencich	2c46513837	Update designs	2019-09-23 18:21:54 -07:00
Alex Forencich	835abf9412	Remove pcie_us_axi_master instances and corresponding BAR	2019-09-19 17:31:59 -07:00
Alex Forencich	b5868c8997	Update PTP perout support in VCU108 and VCU118 designs	2019-09-18 19:46:45 -07:00
Alex Forencich	132d44cd90	Increase crossbar threads count	2019-09-11 18:06:14 -07:00
Alex Forencich	d67c9ff70e	Pull out scheduler op table size parameter	2019-08-23 07:44:33 -07:00
Alex Forencich	744ac22c75	Normalize queue op table sizes	2019-08-22 19:19:51 -07:00
Alex Forencich	6a354e7aa3	Normalize descriptor table sizes	2019-08-22 19:03:19 -07:00
Alex Forencich	a4132cfda7	Integrate TX checksum offload	2019-08-22 00:45:09 -07:00
Alex Forencich	94c8dabad6	Rewrite scheduler	2019-08-13 00:45:01 -07:00
Alex Forencich	80f06e1fcc	Update testbenches	2019-08-13 00:39:28 -07:00
Alex Forencich	2fbbfb05f9	Parametrize channel assignments	2019-07-28 16:02:54 -07:00
Alex Forencich	26f6774182	Parameter updates and documentation	2019-07-27 23:47:46 -07:00
Alex Forencich	958aec8e8c	Add VCU108 mqnic design	2019-07-25 17:05:56 -07:00